Claude review: drm/omap: dsi: avoid sending bta sync all the time in writes

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Positive aspects:**

- The rationale is clear and the problem is well-explained: TC358762 needs configuration before it can transmit, so BTA sync during early writes fails.
- Waiting for `DSI_VC_IRQ_PACKET_SENT` on long packets is the right approach to prevent FIFO overflows without requiring a round-trip BTA.
- The `_dsi_send_nop` removal is correct — it was only called from `dsi_update_channel` and its real purpose was the BTA sync side-effect. Replacing it with a direct `dsi_vc_send_bta_sync()` is cleaner and more explicit.
- The conditional BTA based on `MIPI_DSI_MSG_REQ_ACK` is the right abstraction.

**Issues:**

1. **Typo in TODO comment** (line 2225 of patched file):
   ```c
   /* TODO: find out if more needs to be done for MIPI_DIS_MSG_REQ_ACK */
   ```
   Should be `MIPI_DSI_MSG_REQ_ACK` (not `MIPI_DIS_MSG_REQ_ACK`). This is a transposition of "DSI" → "DIS".

2. **Race between PACKET_SENT IRQ and ISR registration** (lines 2204–2213): `dsi_vc_send_long()` is called *before* `dsi_register_isr_vc()`. If the long packet completes extremely quickly (or the hardware is fast), the PACKET_SENT IRQ could fire before the ISR is registered, and the completion would never be signalled — resulting in a 500ms timeout and spurious `-EIO`. The existing pattern in `dsi_if_enable` (and the BTA sync code in `dsi_vc_send_bta_sync`) registers the ISR *before* triggering the hardware action. The correct order should be:
   ```c
   r = dsi_register_isr_vc(dsi, vc, dsi_completion_handler,
                            &completion, DSI_VC_IRQ_PACKET_SENT);
   if (r)
       return r;

   r = dsi_vc_send_long(dsi, vc, msg);
   if (r < 0) {
       dsi_unregister_isr_vc(dsi, vc, dsi_completion_handler,
                             &completion, DSI_VC_IRQ_PACKET_SENT);
       return r;
   }
   ```
   This is the same register-before-trigger pattern used in `dsi_vc_send_bta_sync()` at lines 2026–2036.

3. **Short packet early return skips RX_FIFO_NOT_EMPTY check** (line 2202): The early `return` for short packets bypasses the `RX_FIFO_NOT_EMPTY` check at lines 2236–2240. The old code ran that check for all writes. This is likely intentional (short packets without BTA shouldn't produce RX data), but it's worth confirming this is safe — if some panel/bridge does produce unexpected data in the RX FIFO after a short write, it would go undetected and could confuse subsequent reads.

4. **Minor: commit message typos** — "wos" should be "was", and "acually" should be "actually" in line 99 of the mbox:
   ```
   the most relevant part wos the bta sync to acually force low power mode.
   ```

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