Claude review: drm/amdgpu/mes11: fix queue init wptr reset

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**The change:**
```c
-		*(ring->wptr_cpu_addr) = 0;
+		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
```

At `mes_v11_0.c:1311`, in the reset/suspend path of `mes_v11_0_queue_init()`.

**Correctness:** The fix is correct. The normal writer `mes_v11_0_ring_set_wptr()` (line 79) uses `atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr)`, and the reader `mes_v11_0_ring_get_wptr()` (line 97) uses `atomic64_read((atomic64_t *)ring->wptr_cpu_addr)`. Using `atomic64_set()` in the reset path makes the reset consistent with these accessors.

**Fixes tag:** `Fixes: d81d75c99936 ("drm/amdgpu/gfx11: enable kiq to map mes ring")` — this identifies when the queue_init code with the plain store was introduced, which seems reasonable.

**Minor note:** The adjacent `*(ring->rptr_cpu_addr) = 0` is left as a 32-bit store, but this is fine because `mes_v11_0_ring_get_rptr()` (line 89) reads rptr via `return *ring->rptr_cpu_addr` — also a 32-bit access — so the rptr path is internally consistent at 32 bits.

**No issues with this patch.**

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