Claude review: drm/panel: simple: Add Startek KD070HDFLD092 LVDS panel support

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Good**

This adds the `display_timing` and `panel_desc` structures plus the `of_device_id` entry.

**Timing validation:**

```c
static const struct display_timing startek_kd070hdfld092_timing = {
	.pixelclock = { 40800000, 51200000, 67200000 },
	.hactive = { 1024, 1024, 1024 },
	.hfront_porch = { 40, 160, 216 },
	.hback_porch = { 30, 140, 140 },
	.hsync_len = { 20, 20, 20 },
	.vactive = { 600, 600, 600 },
	.vfront_porch = { 2, 12, 177 },
	.vback_porch = { 5, 20, 20 },
	.vsync_len = { 3, 3, 3 },
	.flags = DISPLAY_FLAGS_DE_HIGH,
};
```

- Typical totals: H = 1024+160+140+20 = 1344, V = 600+12+20+3 = 635. At 51.2 MHz: 51200000/(1344*635) = ~60 Hz. Correct.
- Min totals: H = 1114, V = 610. At 40.8 MHz: 40800000/(1114*610) = ~60 Hz. Consistent.
- Max totals: H = 1400, V = 800. At 67.2 MHz: 67200000/(1400*800) = 60 Hz. Consistent.
- All three corners converge on 60 Hz, which is expected.

**Panel descriptor:**

```c
static const struct panel_desc startek_kd070hdfld092 = {
	.timings = &startek_kd070hdfld092_timing,
	.num_timings = 1,
	.bpc = 8,
	.size = {
		.width = 154,
		.height = 86,
	},
	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
	.connector_type = DRM_MODE_CONNECTOR_LVDS,
};
```

- `bpc = 8` with `MEDIA_BUS_FMT_RGB888_1X7X4_SPWG` is correct and will pass the validation check at `panel-simple.c:644`.
- `DRM_BUS_FLAG_DE_HIGH` is consistent with the timing `DISPLAY_FLAGS_DE_HIGH`.
- `DRM_MODE_CONNECTOR_LVDS` is correct for an LVDS panel.
- No power-on delays are specified, which is fine -- many LVDS panels in this driver omit them (e.g. the AUO panels around line 814).
- Physical dimensions (154x86 mm) yield a diagonal of ~176 mm / 6.94", confirming the 7" specification.

**of_device_id table:** The new entry is inserted in correct alphabetical order between `starry,kr070pe2t` and `startek,kd070wvfpa`.

No issues.

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