Claude review: drm/rockchip: dw_hdmi_qp: Implement .{enable|disable}_hpd() PHY ops

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This is a significant refactoring of the interrupt handling code.

**Key observation on RK3588 enable_hpd vs old setup_hpd**: The original `setup_hpd` wrote both CLR and MSK=0 in a single register write. The new `enable_hpd` does exactly the same — clear and unmask. Good.

**RK3576 `enable_hpd` does NOT write `0xa404`**: The old `setup_hpd` for RK3576 wrote to `0xa404` (a magic register). The new code moves this write to `io_init()`, which is correct since it's a one-time hardware initialization.

**Interrupt clear in threaded handler**: The old RK3588 threaded handler explicitly cleared the interrupt before re-enabling it. The new code calls `enable_hpd()`, which clears+unmasks atomically. The old RK3576 threaded handler similarly cleared then unmasked. Now both call their respective `enable_hpd()` which does both. This is functionally equivalent and cleaner.

**One subtle issue**: In `dw_hdmi_qp_rk3588_irq` (the threaded handler), the old code did:
```c
val = FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_CLR, 1);  // CLR only
regmap_write(..., val);
// ...
val |= FIELD_PREP_WM16(RK3588_HDMI1_HPD_INT_MSK, 0); // CLR+MSK
regmap_write(..., val);
```
It cleared first, then later wrote CLR+MSK=0 in a second write. The new `enable_hpd` does both in one write. Since these are write-mask-16 registers (upper 16 bits are write-enable, lower 16 bits are the value), combining CLR and MSK into a single write is fine and may even be slightly better to avoid a transient state.

---
Generated by Claude Code Patch Reviewer