Claude review: drm/bridge: dw-hdmi-qp: Add HDMI 2.0 SCDC scrambling support`

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This is the main driver-level implementation patch.

1. **`curr_conn` lifetime**: The `curr_conn` pointer is set in `atomic_enable` and cleared in `atomic_disable`. It is used in `dw_hdmi_qp_hpd_notify()` (patch 14) to decide which HPD notification path to take. There's a potential race if an HPD interrupt fires during `atomic_disable` after `curr_conn` is set to NULL but before the PHY is disabled. However, the HPD interrupt handler only schedules deferred work, so by the time the work runs, the state should be consistent.

2. **Scrambling before PHY init**: In `atomic_enable`, `drm_scdc_start_scrambling()` is called *before* `hdmi->phy.ops->init()`. This sets up the sink-side SCDC configuration and source-side scrambling before the PHY is initialized. The HDMI 2.0 spec requires TMDS clock to be suspended while changing clock ratio, so starting scrambling before PHY init (while clock is still off) is correct.

3. **Error path in atomic_enable**: If `drm_scdc_start_scrambling()` fails, a warning is logged but the enable continues. This is reasonable — you'd rather attempt to display something than fail silently.

4. **HDMI20_MAX_TMDSRATE = 600MHz**: This correctly caps the TMDS rate at the HDMI 2.0 maximum (600 MHz), above which HDMI 2.1 FRL would be needed.

5. **Copyright addition**: Amazon copyright is added alongside Collabora and Rockchip. This appears legitimate given the contribution.

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