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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm: lcdif: Wait for vblank before disabling DMA
Date: Tue, 31 Mar 2026 16:48:35 +1000	[thread overview]
Message-ID: <review-patch3-20260330224619.2620782-4-paulk@sys-base.io> (raw)
In-Reply-To: <20260330224619.2620782-4-paulk@sys-base.io>

Patch Review

This is the actual bug fix. Two issues:

**1. Malformed `Co-developed-by` tag (must fix):**

The trailer has:
```
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Co-developed-by: Lucas Stach <l.stach@pengutronix.de>
```

Per `Documentation/process/submitting-patches.rst`, every `Co-developed-by` **must** be immediately followed by a `Signed-off-by` from that same person. The correct form would be:

```
Co-developed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
```

(The patch author's `Signed-off-by` should generally come last.)

**2. Duplicate error message (should fix):**

```c
if (ret)
    drm_err(lcdif->drm, "Failed to disable controller!\n");
```

This exact same string appears for both the existing `CTRLDESCL0_5_EN` poll timeout and the new `CTRLDESCL0_5_SHADOW_LOAD_EN` poll timeout. If either fails, the log gives no indication of *which* step timed out. The new message should be distinct, e.g., `"Failed to wait for shadow load completion!\n"` or `"Timed out waiting for DMA frame completion!\n"`.

**3. Approach observation (minor):**

The technique of setting `SHADOW_LOAD_EN` and polling for hardware to clear it as a proxy for "frame DMA is complete" is clever. The comment in the code explains the rationale well. The 36000 µs timeout (~2 frames at 60 Hz) matches the existing timeout above and is reasonable.

One subtle question: after the first poll confirms `CTRLDESCL0_5_EN` is cleared, is the hardware guaranteed to still process a `SHADOW_LOAD_EN` request? If `EN` being cleared means the layer is fully off, the shadow load might never be consumed. This deserves verification against the hardware reference or NXP BSP behavior — though the fact that the NXP BSP uses a similar (if cruder) approach with a 25 ms sleep suggests the hardware does honor it.

---
Generated by Claude Code Patch Reviewer

  reply	other threads:[~2026-03-31  6:48 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-30 22:46 [PATCH 0/3] drm: lcdif: FIFO underrun/solid color bug fix Paul Kocialkowski
2026-03-30 22:46 ` [PATCH 1/3] drm: lcdif: Set undocumented bit to clear FIFO at vsync Paul Kocialkowski
2026-03-31  6:48   ` Claude review: " Claude Code Review Bot
2026-03-30 22:46 ` [PATCH 2/3] drm: lcdif: Use dedicated set/clr registers for polarity/edge Paul Kocialkowski
2026-03-31  6:48   ` Claude review: " Claude Code Review Bot
2026-03-30 22:46 ` [PATCH 3/3] drm: lcdif: Wait for vblank before disabling DMA Paul Kocialkowski
2026-03-31  6:48   ` Claude Code Review Bot [this message]
2026-03-31  6:48 ` Claude review: drm: lcdif: FIFO underrun/solid color bug fix Claude Code Review Bot

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