Claude review: gpu: nova-core: add interrupt controller register definitions

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

```rust
pub(crate) NV_VF_INTR_LEAF(u32)[16] @ 0x00b81000 {}
pub(crate) NV_VF_INTR_LEAF_EN_SET(u32)[16] @ 0x00b81200 {}
pub(crate) NV_VF_INTR_LEAF_EN_CLEAR(u32)[16] @ 0x00b81400 {}
pub(crate) NV_VF_INTR_TOP(u32) @ 0x00b81600 {}
pub(crate) NV_VF_INTR_TOP_EN_SET(u32) @ 0x00b81608 {}
pub(crate) NV_VF_INTR_TOP_EN_CLEAR(u32) @ 0x00b81610 {}
pub(crate) NV_VF_INTR_LEAF_TRIGGER(u32) @ 0x00b81640 {}
```

Well documented register definitions. The comments explain the W1C semantics and array sizing clearly.

**Observation:** The register arrays are declared as `[16]` to cover the Hopper/Blackwell maximum. The `IntrCtrl` struct (patch 5) handles the arch-dependent active count via `subtree_mask`. This is fine - reading unused registers on pre-Hopper just returns 0 per the documentation.

**Nit:** The spacing between TOP (0x00b81600), TOP_EN_SET (0x00b81608), and TOP_EN_CLEAR (0x00b81610) shows 8-byte stride, which seems like these are 64-bit registers accessed as 32-bit. The definitions treat them as u32, which is correct for MMIO, but worth noting the layout gap.

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Generated by Claude Code Patch Reviewer