[PATCH 0/5] drm/rockchip: vop2: Fix layer cfg done timeout on multi-output setups

[Cristian Ciocaltea <cristian.ciocaltea@collabora.com>]

On RK3588/RK3568 boards with multiple active display outputs, start/stop
transitions may trigger a timeout during overlay layer configuration:

  rockchip-drm display-subsystem: [drm] *ERROR* wait layer cfg done timeout

The shared OVL_LAYER_SEL and OVL_PORT_SEL shadow registers are committed
to the active configuration at the vsync of whichever Video Port is
selected by LAYERSEL_REGDONE_SEL.  When two Video Ports race through
atomic commits, rk3568_vop2_setup_layer_mixer() has two issues that
cause the wait to poll for a value the hardware might not be able to
produce.

Patch 1 fixes passing the wrong target to the wait function, since the
expected value was already overwritten with the current VP's new
layer_sel before reaching the wait.

Patch 2 moves the wait before the LAYERSEL_REGDONE_SEL switch, so the
previous VP's vsync can still latch the pending configuration.

Patches 3 through 5 contain only minor follow-up cleanup.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
Cristian Ciocaltea (5):
      drm/rockchip: vop2: Fix wrong wait target in layer cfg done check
      drm/rockchip: vop2: Wait for layer cfg done before switching LAYERSEL_REGDONE_SEL
      drm/rockchip: vop2: Delay old_{layer|port}_sel updates in setup_layer_mixer()
      drm/rockchip: vop2: Drop redundant zero-init in setup_layer_mixer()
      drm/rockchip: vop2: Use vop2->old_layer_sel directly in wait_for_layer_cfg_done()

 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 46 +++++++++++++---------------
 1 file changed, 22 insertions(+), 24 deletions(-)
---
base-commit: d4c14903bf5e28e740516c4fbb7db01e0dedf3af
change-id: 20260504-vop2-layer-cfg-tmout-73617a0a103c