From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/disp/dpu: consider SSPP line width during mode valid
Date: Tue, 31 Mar 2026 17:55:49 +1000 [thread overview]
Message-ID: <review-overall-20260328-msm-next-v1-1-12ac4e27c670@oss.qualcomm.com> (raw)
In-Reply-To: <20260328-msm-next-v1-1-12ac4e27c670@oss.qualcomm.com>
Overall Series Review
Subject: drm/msm/disp/dpu: consider SSPP line width during mode valid
Author: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Patches: 6
Reviewed: 2026-03-31T17:55:49.647743
---
This is a single patch that adds SSPP (Source Surface Pixel Processor) line width as an additional constraint during mode validation in the DPU CRTC. The intent is correct — several Qualcomm targets (sm6150, sm6125, sm6115, qcm2290, sm6375) have `max_linewidth` smaller than `max_mixer_width` (e.g., sm6150: max_linewidth=2160, max_mixer_width=2560), meaning modes could pass `dpu_crtc_mode_valid()` but fail later in `atomic_check`.
The code change itself is clean and straightforward. However, there is a gap in the fix.
---
Generated by Claude Code Patch Reviewer
prev parent reply other threads:[~2026-03-31 7:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-28 17:15 [PATCH] drm/msm/disp/dpu: consider SSPP line width during mode valid Vishnu Saini
2026-03-29 0:24 ` Dmitry Baryshkov
2026-03-30 18:30 ` Vishnu Saini
2026-03-30 18:39 ` Dmitry Baryshkov
2026-03-30 18:57 ` Vishnu Saini
2026-03-30 19:38 ` Dmitry Baryshkov
2026-03-31 7:55 ` Claude review: " Claude Code Review Bot
2026-03-31 7:55 ` Claude Code Review Bot [this message]
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