Claude review: drm/i915/reset: Solve display vs. GPU reset deadlock, again

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Overall Series Review

Subject: drm/i915/reset: Solve display vs. GPU reset deadlock, again
Author: Ville Syrjala <ville.syrjala@linux.intel.com>
Patches: 17
Reviewed: 2026-04-12T12:04:47.160621

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This is a well-structured 6-patch series from Ville Syrjälä that re-solves the display vs. GPU reset deadlock in i915. The original fix was lost when `i915_sw_fence` was replaced with `dma_fence` interfaces. The approach is sound: introduce a custom `dma_fence` ("reset fence") that gets signaled just before GPU reset, so that `intel_atomic_commit_fence_wait()` can use `dma_fence_wait_any_timeout()` to wait on whichever signals first — the real plane fence or the reset fence. This avoids the deadlock where the commit blocks on a fence that will never signal because the GPU is hung, while the reset code is trying to acquire modeset locks held by the commit path.

The series is logically decomposed into good preparatory steps: doc fix, refactoring the return value and `HAS_DISPLAY` checks, moving `pending_fb_pin` to i915-specific code, adding xe compat stubs, implementing the actual fence mechanism, and finally switching to an infinite timeout.

**Key concerns:**
1. Patch 3 has a subtle regression in the overlay pin/unpin tracking.
2. Patch 5 has a race window where the reset fence could be discarded before waiters observe signaling.
3. Patch 6 is explicitly experimental per its own commit message, which is fine for CI testing but should not be merged as-is.

Overall the series is a good direction. A few issues need addressing before merge.

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