From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/amdgpu: replace PASID IDR with XArray
Date: Tue, 31 Mar 2026 17:18:18 +1000 [thread overview]
Message-ID: <review-patch1-20260330113501.25654-1-mikhail.v.gavrilov@gmail.com> (raw)
In-Reply-To: <20260330113501.25654-1-mikhail.v.gavrilov@gmail.com>
Patch Review
**Commit message quality:** Excellent. The two bugs are clearly described, the hardirq call chain is documented, and the real-world trigger scenario (RX 7900 XTX + Vulkan/Proton) is mentioned. The Fixes/Cc-stable tags are correct.
**Code review:**
The XArray conversion is mechanically correct:
- `DEFINE_XARRAY_ALLOC` is the right macro for an XArray that will use `xa_alloc` / `__xa_alloc_cyclic`.
- The `static u32 amdgpu_pasid_xa_next` cursor for cyclic allocation is correct — `__xa_alloc_cyclic` requires a caller-managed `next` variable.
- `xa_lock_irqsave` / `xa_unlock_irqrestore` properly handles the hardirq context issue (bug #2).
- `GFP_ATOMIC` is correct since allocation happens under the xa_lock (bug #1 fix).
- `xa_mk_value(0)` as the stored entry is fine — XArray treats `NULL` as "empty slot", so a non-NULL value is needed to mark the PASID as allocated. Using an internal value entry avoids memory allocation for the stored pointer.
- The limit `XA_LIMIT(1, (1U << bits) - 1)` correctly maps the old IDR range `[1, 1U << bits)` — IDR's `end` parameter is exclusive while XA_LIMIT's max is inclusive, so `(1U << bits) - 1` is the right translation.
**Minor nit on return value handling:**
```c
r = __xa_alloc_cyclic(&amdgpu_pasid_xa, &pasid, xa_mk_value(0),
XA_LIMIT(1, (1U << bits) - 1),
&amdgpu_pasid_xa_next, GFP_ATOMIC);
xa_unlock_irqrestore(&amdgpu_pasid_xa, flags);
if (r >= 0) {
trace_amdgpu_pasid_allocated(pasid);
return pasid;
}
return r;
```
`__xa_alloc_cyclic` returns 0 on success, 1 if it wrapped around (both >= 0), or a negative errno. The `r >= 0` check is correct. However, note that `__xa_alloc_cyclic` can return 1 when the allocation wrapped, which is not an error — the code handles this correctly since `r >= 0` covers both cases. Good.
**Cleanup function:**
```c
void amdgpu_pasid_mgr_cleanup(void)
{
xa_destroy(&amdgpu_pasid_xa);
}
```
`xa_destroy()` does not require external locking — it frees internal nodes and resets the array. This is correct and simpler than the IDR version which took the spinlock around `idr_destroy()`. At cleanup time there should be no concurrent access anyway.
**No issues found.** The patch is a clean, correct conversion that fixes both bugs. The only potential concern is that `GFP_ATOMIC` is more restrictive than `GFP_KERNEL` (could fail under memory pressure), but this is unavoidable when allocating under a lock that may be taken in IRQ context, and PASID allocation failures are already handled by callers.
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-31 7:18 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-30 11:35 [PATCH v3] drm/amdgpu: replace PASID IDR with XArray Mikhail Gavrilov
2026-03-30 13:10 ` Lazar, Lijo
2026-03-31 7:18 ` Claude Code Review Bot [this message]
2026-03-31 7:18 ` Claude review: " Claude Code Review Bot
-- strict thread matches above, loose matches on Subject: below --
2026-03-30 14:50 [PATCH v4] " Mikhail Gavrilov
2026-03-31 7:08 ` Claude review: " Claude Code Review Bot
2026-03-31 7:08 ` Claude Code Review Bot
2026-03-30 19:11 [PATCH v5] " Mikhail Gavrilov
2026-03-31 6:57 ` Claude review: " Claude Code Review Bot
2026-03-31 6:57 ` Claude Code Review Bot
2026-03-31 11:17 [PATCH v6] " Mikhail Gavrilov
2026-03-31 21:48 ` Claude review: " Claude Code Review Bot
2026-03-31 21:48 ` Claude Code Review Bot
2026-03-31 14:21 [PATCH v7] " Mikhail Gavrilov
2026-03-31 21:43 ` Claude review: " Claude Code Review Bot
2026-03-31 21:43 ` Claude Code Review Bot
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