Claude review: accel/ivpu: Fix swapped register names in pwr_island_drive functions

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Assessment: Correct, no issues.**

The fix is a clean symmetric swap. In `pwr_island_drive_37xx`:
```c
-	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
```
and the field name changes from `CSS_CPU` to `MSS_CPU` (matching the 37xx header definition). In `pwr_island_drive_40xx`, the inverse swap is applied.

I verified in the register definition headers:
- `ivpu_hw_37xx_reg.h:98`: `VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0 = 0x00030024u` with `MSS_CPU_MASK = BIT_MASK(3)`
- `ivpu_hw_40xx_reg.h:107`: `VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0 = 0x00030024u` with `CSS_CPU_MASK = BIT_MASK(3)`

The `REG_SET_FLD` / `REG_CLR_FLD` macros in `ivpu_hw_reg_io.h` concatenate `REG##_##FLD##_MASK` to form the mask name, so the register name and field name must be from the same generation's header. Before this patch they happened to work only because the offsets and bit positions are identical across generations.

**Minor notes:**
- The commit message could mention a `Fixes:` tag pointing to the commit that introduced the bug, which helps stable-tree backport tracking. However, since the bug is cosmetic, this is not strictly necessary.
- No functional change — safe to apply as-is.

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