Claude review: drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Correctness**: The fix is sound. The `ADV7511_REG_INT(0)` register (address 0x96) uses write-1-to-clear semantics — writing `ADV7511_INT0_HPD` (BIT(7)) clears only the HPD status bit without affecting other interrupt status bits. This is consistent with how the driver already clears interrupts in `adv7511_irq_process()`:

```c
regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
```

and in `adv7511_hpd()`:

```c
regmap_write(adv7511->regmap, ADV7511_REG_INT(0), ADV7511_INT0_HPD);
```

**Placement**: Correct. The clear happens after `adv7511_power_on()`, which powers up the chip and re-enables interrupt generation via `ADV7511_REG_INT_ENABLE(0)`, but does not itself clear any pending status bits. Clearing after power-on ensures the chip is responsive to the register write.

**Scope**: The patch clears only the HPD bit, not other potential stale interrupt bits (EDID_READY, DDC_ERROR, etc.). This is reasonable — HPD is the one specifically reported as causing problems. If other stale interrupts turn out to be an issue, a follow-up could clear all of INT(0) and INT(1), but there's no reason to over-broaden the fix now.

**Minor observation**: The comment is slightly verbose at 4 lines for what is a single write-1-to-clear operation, but it does explain the *why* (stale state across power loss), which is the right kind of comment to include since the reason isn't obvious from the code alone.

**No issues found.** The patch is a clean, minimal, well-targeted fix.

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Generated by Claude Code Patch Reviewer