Claude review: drm/v3d: Wait for pending L2T flush before cleaning caches

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Purpose:** On pre-V3D 7.1 hardware, `v3d_clean_caches()` writes to `V3D_CTL_L2TCACTL` without first checking if a prior L2T flush (`V3D_L2TCACTL_L2TFLS`) is still in flight. This can clobber bits in the register and cause cache inconsistencies.

**Code added in `v3d_gem.c:209-215`:**
```c
/* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */
if (v3d->ver < V3D_GEN_71) {
    if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
                   V3D_L2TCACTL_L2TFLS), 100)) {
        drm_err(dev, "Timeout waiting for L2T clean\n");
    }
}
```

**Analysis:**
- The GFXH-1897 workaround reference is good practice for hardware errata.
- The version guard (`v3d->ver < V3D_GEN_71`) is appropriate — the comment in `v3d_flush_l2t()` at line 179 already notes the L2TFLS busy-bit behavior, and this new wait ensures the previous flush has drained before a clean overwrites the register.
- The 100ms timeout is consistent with all other `wait_for` calls in this file.
- The placement before the `V3D_L2TCACTL_TMUWCF` write is correct — it protects the first write to L2TCACTL.
- The Fixes tag points to the original compute dispatch commit that introduced `v3d_clean_caches`, which is correct — this is a pre-existing bug independent of PM.
- The `Cc: stable@vger.kernel.org` is appropriate.

**Minor note:** The error message "Timeout waiting for L2T clean" could be confused with the identical message at line 231 (the later L2TFLS clean wait). Consider making this one distinct, e.g., "Timeout waiting for pending L2T flush" — but this is cosmetic and not blocking.

**Verdict: Looks correct.**

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Generated by Claude Code Patch Reviewer