Claude review: drm/rockchip: dsi: Add maximum per lane bit rate calculation

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Looks good overall**

This patch replaces the hard-coded max lane rate (previously derived from `dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps`, which was always 1500 Mbps) with a per-chip `max_bit_rate_per_lane` field. The values assigned per SoC are:
- PX30, RK3128, RV1126: 1000 Mbps (1000000000UL)
- RK3568: 1200 Mbps (1200000000UL)
- RK3288, RK3368, RK3399, RK3506: 1500 Mbps (1500000000UL)

The unit conversion is correct:
```c
max_mbps = dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC;
```
`USEC_PER_SEC` = 1,000,000, so e.g. 1,500,000,000 / 1,000,000 = 1500 Mbps. This is correct.

**Minor observation**: For chips that previously had a max of 1500 from `dppa_map`, this is a no-op. For PX30/RK3128/RV1126, this is now a *functional change* that lowers the max from 1500 to 1000 Mbps — this will cause the "out of range" error path to trigger earlier on those chips, which is actually the correct behavior since they can't actually drive 1500 Mbps.

No issues found in this patch.

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