Claude review: drm/rockchip: dsi: Relax the lane rate margin requirements

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Looks correct, accept with caveats**

Changes the overhead factor from `10/8` (25% margin, i.e. 1/0.8) to `10/9` (~11% margin, i.e. 1/0.9) in two places:

```c
/* Internal PHY path */
tmp = mpclk * (bpp / lanes) * 10 / 9;

/* External PHY path */
phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 9,
				 bpp, lanes,
				 &dsi->phy_opts.mipi_dphy);
```

The commit message gives a concrete justification: RGB888 at 148.5 MHz with 4 lanes at 1/0.8 overhead = 1113.75 Mbps, which exceeds the 1000 Mbps limit on PX30/RK3128/RV1126. With 1/0.9, it becomes ~990 Mbps, which fits.

**Concerns:**

- The MIPI DSI spec recommends that the data rate should exceed the required bandwidth to account for protocol overhead (LP escape, ECC, CRC, etc.). 11% margin is tighter than typical. The commit message says "downstream test results" validate this, but it would be helpful to know on which panels/SoCs this was tested.
- The comment `/* since mbps must big than bandwidth of RGB */` (grammar aside) is retained but the meaning changes — the margin is now significantly tighter.
- This is ordered as patch 3/3, so it depends on patch 1 having already set the correct per-chip max. The combination works: chips limited to 1000 Mbps can now drive 148.5 MHz RGB888 panels, which was the motivating use case.

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## SUMMARY

| Patch | Verdict |
|-------|---------|
| 1/3 — max lane bit rate | **OK** |
| 2/3 — dphy_get_timing | **BUG: rk3506_chip_data missing `.dphy_get_timing` — will NULL deref** |
| 3/3 — relax margin | **OK with caveat** (tighter margin; needs tested panel coverage noted) |

The series should not be merged until `rk3506_chip_data` gets its `.dphy_get_timing` assignment added (likely `dw_mipi_dsi_phy_px30_get_timing`).

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Generated by Claude Code Patch Reviewer