Claude review: drm/msm/a6xx: Append SEL regs to dyn pwrup reglist

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This is the most complex patch. Key change: `a6xx_perfcntr_configure()` now appends SEL register programming to the pwrup reglist so GMU can restore them on IFPC exit.

**`cpu_gpu_lock` flex array change**: Changing `regs[62]` to `regs[]` is correct since `PWRUP_REGLIST_SIZE` now determines the actual size.

**Barrier usage**: Two `dma_wmb()` calls - one before modifying SEL entries (after clearing `dynamic_list_len`) and one after writing entries (before updating `dynamic_list_len` to include them). This is correct - it ensures the CP/GMU sees a consistent view.

**Overflow check**: `WARN_ON_ONCE(reglist > (uint32_t *)((uint8_t *)lock + PWRUP_REGLIST_SIZE))` correctly validates we don't overflow the allocated buffer.

**Race with IFPC**: The comment explains that even if we lose the race with SQE restoring registers from the old list, the ringbuffer programming will correct the SEL regs before sampling begins. This reasoning is sound.

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