Claude review: arm64: dts: qcom: Add GPU support for Kaanapali

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Node ordering issue**

This is the main patch adding the GPU and GMU nodes. The GPU node at `gpu@3d00000` and GMU node at `gmu@3d6c000` are both well-structured and follow modern Adreno DT conventions.

**Node ordering problem:** The patch inserts both `gpu@3d00000` and `gmu@3d6c000` before the existing `gxclkctl@3d64000` node:

```diff
+		gpu: gpu@3d00000 {
             ...
+		gmu: gmu@3d6c000 {
             ...
 		gxclkctl: clock-controller@3d64000 {
```

The correct address-sorted order should be:
1. `gpu@3d00000`
2. `gxclkctl@3d64000` (existing)
3. `gmu@3d6c000`

The `gmu` node (0x3d6c000) should be placed **after** `gxclkctl` (0x3d64000), not before it. DT convention is to sort sibling nodes by unit address.

**GPU node details** - all look correct:
- Compatible `"qcom,adreno-44050a01", "qcom,adreno"` matches the binding update in patch 2
- Two reg regions (`kgsl_3d0_reg_memory` at 0x6c000 size, `cx_mem` at 0x2000 size) — consistent with the reg layout conditional in the binding
- `iommus = <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>` — two IOMMU contexts with SID 0x0 (newer pattern vs 0x400 on older SoCs)
- OPP table ranges from 222MHz to 1.3GHz with proper speed-bin masking (`opp-supported-hw` narrows from 0x0f to 0x03 at the top bins)
- `#cooling-cells = <2>` for thermal integration in patch 6
- Interconnect path to `mc_virt SLAVE_EBI1` for memory bandwidth voting

**GMU node details:**
- Compatible `"qcom,adreno-gmu-840.1", "qcom,adreno-gmu"` — follows naming convention
- Single reg region ("gmu") only — older SoCs (sm8450) had three regions (gmu, rscc, gmu_pdc). This appears intentional for the A8xx architecture but is worth confirming with the author
- 5 clocks (ahb, gmu, cxo, memnoc, hub) — reasonable for this generation
- Power domains reference both `GPU_CC_CX_GDSC` and `GX_CLKCTL_GX_GDSC` — the GX domain uses the gxclkctl rather than gpucc, which is a newer pattern seen on recent Qualcomm SoCs
- GMU OPP table has 5 frequency points from 475MHz to 750MHz

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Generated by Claude Code Patch Reviewer