Claude review: arm64: dts: renesas: Add Renesas R-Car V4H DSC

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Looks good**

The DTS changes correctly insert the DSC between DU and DSI1 at the SoC level:

```
DU port@1 (du_out_dsi1) → DSC port@0 (dsc_in_dsi1)
DSC port@1 (dsc_out_dsi1) → DSI1 port@0 (dsi1_in)
```

The DSC node is `status = "disabled"` by default, and the Sparrow Hawk board enables it:

```c
+&dsc {
+	status = "okay";
+};
```

This is correct because the hardware requires DSC to be enabled for DSI1 to work. Any board using DSI1 on this SoC must enable the DSC node.

The DSC node properties (reg, interrupts, clocks, power-domains, resets) match both the DT binding (patch 2) and the driver's resource acquisition (patch 3). The clock and reset module IDs (2819) match the clock entry added in patch 1.

The comment `/* Page 27 / DSI to Display */` on the `&dsc` block matches the existing convention in the board file for `&dsi1`.

---

**Summary:** The series is well-structured and the approach is appropriate for enabling bypass-mode DSC. The main actionable item is fixing the error handling in `rcar_dsc_atomic_enable` to not deassert reset when clock enable fails. Everything else is minor or informational.

---
Generated by Claude Code Patch Reviewer