Claude review: drm/msm/adreno: add Adreno 810 GPU support

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This is the main catalog entry patch. Several sub-items:

**adreno_is_a810():** Added in `adreno_gpu.h` but not used anywhere in this series. If no callers are needed yet, consider deferring this addition until it's actually needed to avoid dead code. The pattern does match existing `adreno_is_x285()` and `adreno_is_a840()` helpers though, so adding it preemptively is consistent.

**a810_nonctxt_regs:** The register values look reasonable. A couple of notes:
- `REG_A8XX_GRAS_DBG_ECO_CNTL` is set to `0x00f80800` for A810 vs `0x00000800` for A840 — the extra bits (0x00f80000) are presumably A810-specific hardware requirements.
- `REG_A7XX_SP_CHICKEN_BITS_2` uses `BIT(22) | BIT(23)` — using BIT macros here is cleaner than a hex value. Good.

**a810_protect_regs:** 47 entries with `count_max = 64`. The BUILD_BUG_ON in `__build_asserts` correctly validates 47 <= 64.

**a810_pwrup_reglist_regs:** Includes the UCHE_CCHE_TRAP_BASE and UCHE_CCHE_WRITE_THRU_BASE entries mentioned in the v3 changelog. The `+ 1` pattern for 64-bit register pairs (LO/HI) is standard:

```c
REG_A8XX_UCHE_CCHE_TRAP_BASE,
REG_A8XX_UCHE_CCHE_TRAP_BASE + 1,
```

**a810_ifpc_reglist_regs:** Includes all 64 CP_PROTECT_GLOBAL slots (0-63) as noted in the v3 changelog.

**a810_dyn_pwrup_reglist_regs:** References `REG_A8XX_CP_PROTECT_PIPE(15)`, consistent with the hardcoded slot 15 from patch 5.

**Catalog entry:**
- `family = ADRENO_8XX_GEN1` — makes sense, A810 is gen1 A8xx.
- Firmware names `gen80300_*` match GMU chipid `0x8030000`.
- `gmem = SZ_512K + SZ_64K` (576K) — smaller than A840's GMEM, appropriate for the lower-tier part.
- `max_slices = 1` — appropriate for a single-slice GPU.
- `preempt_record_size = 4558 * SZ_1K` — much smaller than A840's 19708K, consistent with 1 slice vs 3.
- Quirks include `ADRENO_QUIRK_IFPC` but not `ADRENO_QUIRK_SOFTFUSE`, matching A840.
- BCM entries (SH0/16, MC0/4, ACV) look standard.

**Minor:** The entry is placed after the A840 entry but the family is `ADRENO_8XX_GEN1` while A840 is `ADRENO_8XX_GEN2`. It might be more natural to place A810 (GEN1) before the GEN2 entries, but this is cosmetic and shouldn't affect functionality since lookups are by chip_id.

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Generated by Claude Code Patch Reviewer