Claude review: drm/msm/a8xx: Fix RSCC offset

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Patch Review

**Change:** Switches `gmu->rscc` from `gmu->mmio + 0x19000` to `gpu->mmio + 0x50000` for all A8xx GPUs.

This is a correctness fix. The RSCC block on A8xx lives at GPU base + 0x50000 (physical 0x3d50000), inside the GPU's `kgsl_3d0_reg_memory` range, not inside the GMU's register space. The old offset 0x19000 from GMU base (0x3d6c000) would yield physical 0x3d85000 -- a completely different address.

I verified that `gpu->mmio` is initialized before `a6xx_gmu_init()` runs (set in `msm_gpu_init()` called via `adreno_gpu_init()` at `a6xx_gpu.c:2671`, before `a6xx_gmu_init()` at line 2692).

**Minor nit:** The comment has a double space:
```c
		 * On a8xx , RSCC lives at GPU base + 0x50000, which falls
```
Should be `On a8xx,` (no space before comma).

**Question:** This changes behavior for **all** `adreno_is_a8xx()` GPUs (both `ADRENO_8XX_GEN1` / a830 family and `ADRENO_8XX_GEN2` / a840 family). Was the previous offset (gmu->mmio + 0x19000) ever correct for any A8xx part, or was this always wrong? The commit message says "Fix RSCC offset" but doesn't clarify whether existing A8xx support was broken. If the sm8750 A8xx GPU was working before with the old offset, this needs more explanation. If no A8xx board was actually booting Linux before, then this is fine as a pre-emptive fix.

**Verdict:** The change itself is correct in structure (uses the right variable, proper scope). The commit message could mention whether this is a regression fix or a fix for code that was never actually exercised.

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