Claude review: drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Good**

Refactors the hardcoded pixel clock check into per-SoC `mode_clock_min`/`mode_clock_max` fields in `rzg2l_du_device_info`. The old code:

```c
if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
    return MODE_CLOCK_HIGH;
```

becomes a table-driven check with an early return for non-DPAD0 outputs:

```c
if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
    return MODE_OK;

if (info->mode_clock_min && mode->clock < info->mode_clock_min)
    return MODE_CLOCK_LOW;
if (info->mode_clock_max && mode->clock > info->mode_clock_max)
    return MODE_CLOCK_HIGH;
```

The zero-check (`info->mode_clock_min &&`) means SoCs that don't set these fields (like `r9a09g057`) will skip validation, which is correct since that SoC uses DSI0 output only (no DPAD0 route) and the early return would catch it anyway.

Existing RZ/G2UL and RZ/G2L both get `mode_clock_min = 20875` and `mode_clock_max = 83500`, preserving the existing 83500 max and adding the previously missing minimum. The addition of the minimum check is a slight functional change but is reasonable as a correction.

The trailing comma fix on the `r9a07g044` struct is a nice bonus cleanup:
```c
-	}
+	},
```

---
Generated by Claude Code Patch Reviewer