Claude review: drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Correct fix, but deserves a note about the underlying issue**

The existing code uses `protect->count_max` as the pipe protect slot index:

```c
a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
```

For the existing A8xx GPUs (x285 and a840), `count_max` happens to be 15 (via `DECLARE_ADRENO_PROTECT(..., 15)`). But for A810, `count_max` is 64 because A810 has 64 global protect slots. Since pipe protect only has 16 slots (0-15), using `count_max=64` as a pipe slot index would be out of bounds.

The fix hardcodes slot 15, matching the downstream driver. This is correct behavior — the last-span-unbound feature should always target the last pipe slot.

```c
+	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
+	a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
```

**Suggestion**: This patch should ideally come *before* patch 6 (which introduces `DECLARE_ADRENO_PROTECT(a810_protect, 64)`) to avoid any window where the code is broken — though since these patches are applied as a series, bisectability is maintained because the A810 chip ID won't match on any hardware until patch 6 adds the catalog entry.

**Design note**: The fact that `count_max` was accidentally overloaded with two meanings (global slot capacity AND pipe slot index) is a latent bug. It might be worth a follow-up to add a `#define A8XX_PIPE_PROTECT_LAST_SLOT 15` or similar, and perhaps add a comment in `DECLARE_ADRENO_PROTECT` noting that `count_max` for A8xx is the global protect count, not the pipe slot. But that's cleanup, not a blocker.

Has `Reviewed-by` from Konrad Dybcio and Akhil P Oommen.

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