Claude review: drm: renesas: rz-du: Add support for RZ/T2H SoC

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Looks good.**

This patch adds the device info, feature flag, and CRTC modification for RZ/T2H:

```c
+#define RZG2L_DU_FEATURE_DPIO_OE	BIT(0)	/* Has DPIO output enable control */
```

```c
+static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info = {
+	.channels_mask = BIT(0),
+	.routes = {
+		[RZG2L_DU_OUTPUT_DPAD0] = {
+			.possible_outputs = BIT(0),
+			.port = 0,
+			.mode_clock_min = 5000,
+			.mode_clock_max = 100000,
+		},
+	},
+	.features = RZG2L_DU_FEATURE_DPIO_OE,
+};
```

The `rzg2l_du_has()` helper is clean:

```c
+static inline bool rzg2l_du_has(struct rzg2l_du_device *rcdu,
+				unsigned int feature)
+{
+	return rcdu->info->features & feature;
+}
```

The CRTC start/stop modification correctly gates DPI_EN on the feature flag:

```c
+	u32 val = DU_MCR0_DI_EN;
+
+	if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE))
+		val |= DU_MCR0_DPI_EN;
+
+	writel(start ? val : 0, rcdu->mmio + DU_MCR0);
```

The DPI_EN bit is only asserted during start and cleared on stop (val becomes 0). This is correct behavior — the output enable should track the display state.

The clock limits (5–100 MHz) differ from the RZ/G2UL limits (20.875–83.5 MHz), which validates the per-output routing design from patch 4.

Has Reviewed-by from Laurent Pinchart.

**Summary:** The series is well-structured and mostly ready. The main point to address is whether the `if/then/else` pattern for `resets` in the binding (patch 2) follows the preferred DT schema style, or whether keeping `resets` in the global `required` and only adding an `if/then` override for RZ/T2H would be cleaner. The driver changes are correct and well-designed.

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Generated by Claude Code Patch Reviewer