Claude review: drm/xe: Suppress Surprise Link Down on non-hotplug device

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

The rationale is sound: a cold reset drops the PCIe link, and on non-hotplug slots this triggers a spurious Surprise Link Down AER event that defeats the recovery. Masking SLD on the USP before requesting the cold reset prevents this.

**Concern: SLD mask is never restored**

```c
pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, &aer_uncorr_mask);
aer_uncorr_mask |= PCI_ERR_UNC_SURPDN;
pci_write_config_dword(usp, aer_cap + PCI_ERR_UNCOR_MASK, aer_uncorr_mask);
```

If the cold reset succeeds, hardware presumably reinitializes the AER registers, so the mask is implicitly cleared. But if the cold reset is never performed (userspace ignores the uevent) or fails, the SLD mask remains permanently applied on the USP. This means legitimate surprise link-down events would be silently masked for the remaining uptime of the system. Consider documenting this trade-off explicitly, or adding a comment explaining why restoration isn't needed.

**`pcie_slot_is_hotplug_capable()` — correct but worth a comment**

```c
static bool pcie_slot_is_hotplug_capable(struct pci_dev *usp)
{
	struct pci_dev *root_port = pci_upstream_bridge(usp);
```

The function name says "slot" but it takes the USP and walks up to the root port. This is correct (the slot the USP is plugged into is owned by the root port), but the naming could confuse readers. A brief comment like `/* The hotplug slot is on usp's parent (root port) */` would help.

**Hotplug capability check:**

```c
return (sltcap & (PCI_EXP_SLTCAP_HPC | PCI_EXP_SLTCAP_PCP)) ==
	(PCI_EXP_SLTCAP_HPC | PCI_EXP_SLTCAP_PCP);
```

Checking both Hot-Plug Capable and Power Controller Present is correct — both must be present for the slot to support power cycling that would make a surprise link-down expected.

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