Claude review: drm/xe: Suppress Surprise Link Down on non-hotplug device

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

This patch masks the Surprise Link Down AER bit on the upstream switch port before triggering cold reset on non-hotplug slots.

**Naming concern: `pcie_` prefix on static functions**

```c
+static bool pcie_slot_is_hotplug_capable(struct pci_dev *usp)
+static void pcie_suppress_surprise_link_down(struct pci_dev *usp)
```

The `pcie_` prefix is conventionally reserved for PCI core/subsystem functions (defined in `include/linux/pci.h` and `drivers/pci/`). Using it for static driver functions risks confusion. Consider `xe_pcie_` or just descriptive names without the prefix.

**Logic is sound:**

The hierarchy is well-documented in the comment:
```c
	/*
	 * Root Port --> Upstream Switch Port (USP) --> Virtual Switch Port (VSP) --> SGunit
	 *
	 * Cold reset power-cycles the slot, dropping the PCIe link. On a non-hotplug
	 * slot this triggers a spurious Surprise Link Down AER event on the USP.
	 */
```

The check correctly traverses two levels up from the GPU endpoint to reach the USP, then checks the root port (one more level up) for hotplug capability:

```c
+static bool pcie_slot_is_hotplug_capable(struct pci_dev *usp)
+{
+	struct pci_dev *root_port = pci_upstream_bridge(usp);
+	...
+	return (sltcap & (PCI_EXP_SLTCAP_HPC | PCI_EXP_SLTCAP_PCP)) ==
+		(PCI_EXP_SLTCAP_HPC | PCI_EXP_SLTCAP_PCP);
+}
```

This checks both `HPC` (Hot-Plug Capable) and `PCP` (Power Controller Present), which is the right combination for determining if the slot can handle surprise removal gracefully.

**Missing NULL check in the `#ifdef CONFIG_PCIEAER` block:**

```c
+	vsp = pci_upstream_bridge(pdev);
+	usp = vsp ? pci_upstream_bridge(vsp) : NULL;
+
+	if (usp && !pcie_slot_is_hotplug_capable(usp))
+		pcie_suppress_surprise_link_down(usp);
```

The NULL handling for `vsp` and `usp` is correct here. This is fine.

**The mask is never restored**

The Surprise Link Down mask bit is set but never cleared after recovery. If the device is successfully power-cycled and re-probed, the USP's AER configuration will have this bit permanently masked. The `aer_unmask_and_downgrade_internal_error()` function in patch 1 calls `pci_save_state(usp)` after modifying AER registers, but `pcie_suppress_surprise_link_down()` does not. After a cold reset and rescan, the PCI core should restore default AER state, so this may be moot — but it's worth confirming that this is intentional.

---
Generated by Claude Code Patch Reviewer