Claude review: accel/amdxdna: Add AIE4 power on and off support

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

Adds SMU init/fini to the AIE4 firmware load/unload path and NPU3 SMU register definitions.

**Issue 1 — `SMU_ARG_REG` and `SMU_OUT_REG` aliased:**
```c
DEFINE_BAR_OFFSET(SMU_ARG_REG,  NPU3_SMU, MP1_C2PMSG_61_ALT_1),
...
DEFINE_BAR_OFFSET(SMU_OUT_REG,  NPU3_SMU, MP1_C2PMSG_61_ALT_1),
```
Same register for input argument and output. This is the same aliasing pattern as PSP. Appears intentional for the NPU3 hardware protocol.

**Issue 2 — `SMU_INTR_REG` maps to bar base:**
```c
DEFINE_BAR_OFFSET(SMU_INTR_REG, NPU3_SMU, MMNPU_APERTURE4_BASE),
```
`DEFINE_BAR_OFFSET` computes `(reg_addr) - bar##_BAR_BASE`, and here `NPU3_SMU_BAR_BASE = MMNPU_APERTURE4_BASE`, so the offset is 0. The interrupt register is at offset 0 of the SMU BAR. This seems intentional.

**Issue 3 — No DPM reset before `aie_smu_fini` in AIE4:**
```c
static void aie4_fw_unload(struct amdxdna_dev_hdl *ndev)
{
    aie_psp_stop(ndev->aie.psp_hdl);
    aie_smu_fini(ndev->aie.smu_hdl);
}
```
No DPM level reset before power off. If this is intentional (AIE4 doesn't need it), it should be documented. If not, it's a bug.

**Overall the series is a reasonable first step.** The main concerns are: the duplicate struct name pattern, the PSP bisection issue between patches 3 and 4, the `readx_poll_timeout` pointer arithmetic bug in patch 2, and the UAPI device type gap. The register aliasing patterns should be documented for future maintainers.

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