Claude review: drm/panthor: Use a local iomem base for PWR registers

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Good, with one pre-existing bug noted.**

Adds `void __iomem *iomem` to `struct panthor_pwr`, set to `ptdev->iomem + GPU_CONTROL_BASE + PWR_CONTROL_BASE`:

```c
+	pwr->iomem = ptdev->iomem + GPU_CONTROL_BASE + PWR_CONTROL_BASE;
```

Since `GPU_CONTROL_BASE` is 0x0, this effectively becomes `ptdev->iomem + 0x800`, which is correct for the power management register block.

Register defines are rebased — for example, `TILER_PWRTRANS` changes from a `PWR_CTRL_REG()` macro invocation to a plain offset relative to PWR_CONTROL_BASE:

```c
-#define TILER_PWRTRANS			PWR_CTRL_REG(0x18)
+#define TILER_PWRTRANS			0x18
```

The IRQ iomem for PWR is set to `ptdev->iomem + PWR_INT_BASE` where `PWR_INT_BASE` becomes 0x800 (same as `PWR_CONTROL_BASE`). Looking at the Mali register map, the PWR interrupt registers are indeed at offset 0x800 from the GPU base — this is because the PWR_INT registers happen to be at the start of the PWR block. Correct.

**Pre-existing bug (not introduced by this series):** In `panthor_pwr_l2_power_on()`:

```c
 	const u32 pwr_status = gpu_read64(pwr->iomem, L2_PWRTRANS);
```

`gpu_read64` returns `u64`, but the result is stored in a `u32`. This silently truncates the upper 32 bits. For current hardware with ≤32 shader cores this is harmless, but it's technically wrong. This truncation exists in the current code as well — the patch merely changes the iomem argument, not the type. Worth fixing separately.

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