Claude review: gpu: nova-core: gsp: shuffle boot code a bit to keep chipset-specific parts close

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**This patch has a meaningful behavioral change despite the commit message saying "no effect on the GSP boot process."**

The `wpr_meta` allocation is moved earlier (before FWSEC-FRTS), which is fine. But critically, `SetSystemInfo` and `SetRegistry` command sends are moved from **before** the GSP falcon boot to **after** the RISC-V active poll:

```rust
-        self.cmdq
-            .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev))?;
-        self.cmdq
-            .send_command_no_wait(bar, commands::SetRegistry::new())?;
-
         gsp_falcon.reset(bar)?;
         ...
+        self.cmdq
+            .send_command_no_wait(bar, commands::SetSystemInfo::new(pdev))?;
+        self.cmdq
+            .send_command_no_wait(bar, commands::SetRegistry::new())?;
```

These are `send_command_no_wait` calls that enqueue commands for the GSP to process. Previously they were enqueued before the GSP falcon was booted (which implies the command queue is written to shared memory that the GSP reads after boot). Now they're sent after RISC-V is confirmed active.

**This ordering change could matter** — if the GSP reads the command queue immediately upon becoming active, the commands might not be there yet in the new ordering. However, since the sequencer runs after these commands (and the sequencer itself triggers GSP processing), this is likely safe. But the commit message should acknowledge this is a behavioral change, not just a shuffle.

Worth a comment from the author on whether this reordering was tested and is intentional.

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