From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/bridge: tc358762: Update comment about the number of lanes
Date: Sat, 16 May 2026 12:04:23 +1000 [thread overview]
Message-ID: <review-patch7-20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> (raw)
In-Reply-To: <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com>
Patch Review
Replaces the `TODO: Find out how to get dual-lane mode working` with a clear explanation of *why* only 1 lane works: with DSI clock as pixel clock source, the divider is `bitspp / 8 / nlanes`. For RGB888, nlanes=1 gives divider=3, nlanes=2 would need divider=1.5 which isn't possible.
This is a good explanation that saves future developers from going down a rabbit hole. The comment references `SYSCTRL_PCLKDIV_DIV_2` and `SYSCTRL_PCLKDIV_DIV_3` defined in patch 2, making the connection clear.
No issues. **Reviewed-by worthy.**
---
Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-05-16 2:04 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 13:10 [PATCH v3 00/13] drm/bridge: tc358762: Various small fixes Tomi Valkeinen
2026-05-13 13:10 ` [PATCH v3 01/13] drm/bridge: tc358762: Clean up register defines Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 02/13] drm/bridge: tc358762: Improve SYSCTRL " Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 03/13] drm/bridge: tc358762: Improve LCDCTRL defines Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 04/13] drm/bridge: tc358762: Configure SYSCTRL first Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 05/13] drm/bridge: tc358762: Drop SPICMR write Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 06/13] drm/bridge: tc358762: Improve DPI enable handling Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 07/13] drm/bridge: tc358762: Update comment about the number of lanes Tomi Valkeinen
2026-05-16 2:04 ` Claude Code Review Bot [this message]
2026-05-13 13:10 ` [PATCH v3 08/13] drm/bridge: tc358762: Support VTG Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 09/13] drm/bridge: tc358762: Fix sync polarities Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 10/13] drm/bridge: tc358762: Move tc358762_init() into tc358762_enable() Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 11/13] drm/bridge: tc358762: Drop drm_bridge_funcs.mode_set Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 12/13] drm/bridge: tc358762: Set DE_POL and DCLK_POL properly Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 13/13] drm/panel-simple: Fix powertip,ph800480t013-idf02 timings Tomi Valkeinen
2026-05-16 2:04 ` Claude review: " Claude Code Review Bot
2026-05-16 2:04 ` Claude review: drm/bridge: tc358762: Various small fixes Claude Code Review Bot
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