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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/bridge: tc358762: Support VTG
Date: Sat, 16 May 2026 12:04:23 +1000	[thread overview]
Message-ID: <review-patch8-20260513-tc358762-fixes-v3-8-6698b55008b9@ideasonboard.com> (raw)
In-Reply-To: <20260513-tc358762-fixes-v3-8-6698b55008b9@ideasonboard.com>

Patch Review

Adds Video Timing Generator support. When VTG is enabled, the TC358762 generates DPI output timings from its internal registers rather than duplicating DSI input timings. This fixes observed hsync instability.

The implementation:
- Adds VTG register defines (`LCDC_HSR_HBPR`, `LCDC_HDISPR_HFPR`, etc.)
- Converts `drm_display_mode` to `videomode` and programs the timing registers
- Sets `LCDCTRL_VTGEN` and triggers `LCDC_VFUEN` to upload timings
- Adds `use_vtg` flag, hardcoded to `true` in probe

The `use_vtg` field and conditional could be simplified to always-on code since it's hardcoded to `true`, but keeping it as a flag makes the code self-documenting and leaves room for future configurability. This is reasonable.

One observation: `struct videomode vm = { 0 }` — the preferred kernel style is `= { }` or `= {}`, but `= { 0 }` works fine and is common enough.

No issues. **Reviewed-by worthy.**

---
Generated by Claude Code Patch Reviewer

  reply	other threads:[~2026-05-16  2:04 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-13 13:10 [PATCH v3 00/13] drm/bridge: tc358762: Various small fixes Tomi Valkeinen
2026-05-13 13:10 ` [PATCH v3 01/13] drm/bridge: tc358762: Clean up register defines Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 02/13] drm/bridge: tc358762: Improve SYSCTRL " Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 03/13] drm/bridge: tc358762: Improve LCDCTRL defines Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 04/13] drm/bridge: tc358762: Configure SYSCTRL first Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 05/13] drm/bridge: tc358762: Drop SPICMR write Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 06/13] drm/bridge: tc358762: Improve DPI enable handling Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 07/13] drm/bridge: tc358762: Update comment about the number of lanes Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 08/13] drm/bridge: tc358762: Support VTG Tomi Valkeinen
2026-05-16  2:04   ` Claude Code Review Bot [this message]
2026-05-13 13:10 ` [PATCH v3 09/13] drm/bridge: tc358762: Fix sync polarities Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 10/13] drm/bridge: tc358762: Move tc358762_init() into tc358762_enable() Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 11/13] drm/bridge: tc358762: Drop drm_bridge_funcs.mode_set Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 12/13] drm/bridge: tc358762: Set DE_POL and DCLK_POL properly Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-13 13:10 ` [PATCH v3 13/13] drm/panel-simple: Fix powertip,ph800480t013-idf02 timings Tomi Valkeinen
2026-05-16  2:04   ` Claude review: " Claude Code Review Bot
2026-05-16  2:04 ` Claude review: drm/bridge: tc358762: Various small fixes Claude Code Review Bot

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