From: Taniya Das <taniya.das@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
Rob Clark <robin.clark@oss.qualcomm.com>,
Sean Paul <sean@poorly.run>,
Konrad Dybcio <konradybcio@kernel.org>,
Akhil P Oommen <akhilpo@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>
Cc: Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org,
Taniya Das <taniya.das@oss.qualcomm.com>
Subject: [PATCH 1/6] clk: qcom: gdsc: Add custom disable callback for GX GDSC
Date: Tue, 07 Apr 2026 15:00:51 +0530 [thread overview]
Message-ID: <20260407-gfx-clk-fixes-v1-1-4bb5583a5054@oss.qualcomm.com> (raw)
In-Reply-To: <20260407-gfx-clk-fixes-v1-0-4bb5583a5054@oss.qualcomm.com>
From: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
The GX GDSC is a special power domain that should only be disabled
by OS during GMU recovery. In all other scenarios, the GMU firmware
is responsible for handling its disable sequence, and OS must not
interfere.
During the resume_noirq() phase of system resume, the GenPD framework
enables all power domains and later disables them in the complete()
phase if there are no active votes from OS. This behavior can
incorrectly disable the GX GDSC while the GMU firmware is still using
it.
To prevent this, implement a custom disable callback for GX GDSC that
relies on GenPD’s synced_poweroff flag. The GMU driver sets this flag
only during recovery, allowing OS to explicitly disable GX GDSC in
hardware in that case. In all other situations, the disable callback
will avoid touching GX GDSC hardware.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
drivers/clk/qcom/gdsc.c | 22 ++++++++++++++++++++++
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 23 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 95aa071202455421d818171d04f95d15e2b581fa..ab5d741a2e2351bfac06a6814c5a8ba7355bc8bc 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -675,3 +675,25 @@ int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain)
return ret;
}
EXPORT_SYMBOL_GPL(gdsc_gx_do_nothing_enable);
+
+/*
+ * GX GDSC is a special power domain. Normally, its disable sequence
+ * is managed by the GMU firmware, and high level OS must not attempt
+ * to disable it. The only exception is during GMU recovery, where the
+ * GMU driver can set GenPD’s synced_poweroff flag to allow explicitly
+ * disable GX GDSC in hardware.
+ */
+int gdsc_gx_disable(struct generic_pm_domain *domain)
+{
+ struct gdsc *sc = domain_to_gdsc(domain);
+
+ if (domain->synced_poweroff)
+ return gdsc_disable(domain);
+
+ /* Remove parent-supply placed in enable */
+ if (sc->rsupply)
+ return regulator_disable(sc->rsupply);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(gdsc_gx_disable);
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index dd843e86c05b2f30e6d9e978681580016333839d..495daebaf99519ba0571070b41d133ee867c4fd3 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -88,6 +88,7 @@ int gdsc_register(struct gdsc_desc *desc, struct reset_controller_dev *,
struct regmap *);
void gdsc_unregister(struct gdsc_desc *desc);
int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain);
+int gdsc_gx_disable(struct generic_pm_domain *domain);
#else
static inline int gdsc_register(struct gdsc_desc *desc,
struct reset_controller_dev *rcdev,
--
2.34.1
next prev parent reply other threads:[~2026-04-07 9:31 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-07 9:30 [PATCH 0/6] qcom: Refactor GPU GX GDSC handling and IFPC behavior on A8x GPUs Taniya Das
2026-04-07 9:30 ` Taniya Das [this message]
2026-04-07 10:56 ` [PATCH 1/6] clk: qcom: gdsc: Add custom disable callback for GX GDSC Konrad Dybcio
2026-04-08 7:26 ` Taniya Das
2026-04-12 3:46 ` Claude review: " Claude Code Review Bot
2026-04-07 9:30 ` [PATCH 2/6] clk: qcom: gxclkctl: Use custom disable callback for gx_gdsc Taniya Das
2026-04-07 10:56 ` Konrad Dybcio
2026-04-12 3:46 ` Claude review: " Claude Code Review Bot
2026-04-07 9:30 ` [PATCH 3/6] clk: qcom: common: ensure runtime PM suspend completes on probe Taniya Das
2026-04-07 10:58 ` Konrad Dybcio
2026-04-08 7:26 ` Taniya Das
2026-04-12 3:46 ` Claude review: " Claude Code Review Bot
2026-04-07 9:30 ` [PATCH 4/6] clk: qcom: gxclkctl: Remove GX/GMxC rail votes to align with IFPC Taniya Das
2026-04-07 11:29 ` Konrad Dybcio
2026-04-08 7:25 ` Taniya Das
2026-04-12 3:46 ` Claude review: " Claude Code Review Bot
2026-04-07 9:30 ` [PATCH 5/6] drm/msm/a8xx: Make a8xx_recover IFPC safe Taniya Das
2026-04-07 11:00 ` Konrad Dybcio
2026-04-12 3:46 ` Claude review: " Claude Code Review Bot
2026-04-07 9:30 ` [PATCH 6/6] drm/msm/a6xx: Limit GXPD votes to recovery in A8x Taniya Das
2026-04-07 11:01 ` Konrad Dybcio
2026-04-07 19:16 ` Akhil P Oommen
2026-04-12 3:46 ` Claude review: " Claude Code Review Bot
2026-04-12 3:46 ` Claude review: qcom: Refactor GPU GX GDSC handling and IFPC behavior on A8x GPUs Claude Code Review Bot
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