[PATCH v2] drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()

[PATCH v2] drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

On RZ/G3E SMARC EVK, suspend-to-RAM via PSCI powers down the ADV7535
chip entirely, causing the HPD status bit to be in a stale state on
resume. When the display controller driver's system PM resume callback
invokes drm_mode_config_helper_resume(), it calls the bridge's
atomic_enable(), but the stale HPD IRQ is never cleared, leading to
incorrect behaviour.

Clear the HPD status bit in adv7511_bridge_atomic_enable() after
powering on, so that any HPD interrupt latched before or during
power-loss is dismissed before normal operation resumes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Tested HPD, s2idle and s2ram on RZ/G3L SMARC EVK connected to ADV7535
on both polling and IRQ mode.
v1->v2:
 * Dropped PM support instead clearing latched HPD status bit in
   adv7511_bridge_atomic_enable()
 * Dropped suspended variable from struct adv7511.
 * Updated comment in adv7511_bridge_atomic_enable().
 * Clearing the HPD status bit unconditionally as there is no harm.
 * Updated commit header and description.
 * Dropped the tags.
---
 drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
index 6bd76c1fb007..7663814b4032 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
@@ -792,6 +792,13 @@ static void adv7511_bridge_atomic_enable(struct drm_bridge *bridge,
 
 	adv7511_power_on(adv);
 
+	/*
+	 * Clear the HPD status bit (ADV7511_INT0_HPD), so that any HPD
+	 * interrupt latched before or during power loss is dismissed before
+	 * normal operation resumes.
+	 */
+	regmap_write(adv->regmap, ADV7511_REG_INT(0), ADV7511_INT0_HPD);
+
 	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
 	if (WARN_ON(!connector))
 		return;
-- 
2.43.0

Re: [PATCH v2] drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()

[Tommaso Merciai]

Hi Biju,
Thank you for your patch.

On Wed, Apr 22, 2026 at 01:14:54PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> On RZ/G3E SMARC EVK, suspend-to-RAM via PSCI powers down the ADV7535
> chip entirely, causing the HPD status bit to be in a stale state on
> resume. When the display controller driver's system PM resume callback
> invokes drm_mode_config_helper_resume(), it calls the bridge's
> atomic_enable(), but the stale HPD IRQ is never cleared, leading to
> incorrect behaviour.
> 
> Clear the HPD status bit in adv7511_bridge_atomic_enable() after
> powering on, so that any HPD interrupt latched before or during
> power-loss is dismissed before normal operation resumes.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Patch LGTM.

Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Kind Regards,
Tommaso


> ---
> Tested HPD, s2idle and s2ram on RZ/G3L SMARC EVK connected to ADV7535
> on both polling and IRQ mode.
> v1->v2:
>  * Dropped PM support instead clearing latched HPD status bit in
>    adv7511_bridge_atomic_enable()
>  * Dropped suspended variable from struct adv7511.
>  * Updated comment in adv7511_bridge_atomic_enable().
>  * Clearing the HPD status bit unconditionally as there is no harm.
>  * Updated commit header and description.
>  * Dropped the tags.
> ---
>  drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> index 6bd76c1fb007..7663814b4032 100644
> --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c
> @@ -792,6 +792,13 @@ static void adv7511_bridge_atomic_enable(struct drm_bridge *bridge,
>  
>  	adv7511_power_on(adv);
>  
> +	/*
> +	 * Clear the HPD status bit (ADV7511_INT0_HPD), so that any HPD
> +	 * interrupt latched before or during power loss is dismissed before
> +	 * normal operation resumes.
> +	 */
> +	regmap_write(adv->regmap, ADV7511_REG_INT(0), ADV7511_INT0_HPD);
> +
>  	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
>  	if (WARN_ON(!connector))
>  		return;
> -- 
> 2.43.0
> 

Claude review: drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()

[Claude Code Review Bot]

Overall Series Review

Subject: drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()
Author: Biju <biju.das.au@gmail.com>
Patches: 2
Reviewed: 2026-04-23T07:43:34.470013

---

This is a single-patch series fixing a real suspend/resume bug on the RZ/G3E SMARC EVK with the ADV7535 bridge chip. After suspend-to-RAM via PSCI, the chip loses power entirely, and the HPD status bit in `ADV7511_REG_INT(0)` retains a stale latched value on resume. When `drm_mode_config_helper_resume()` calls `atomic_enable()`, this stale bit is never cleared, causing incorrect behavior.

The fix is straightforward and correct: write `ADV7511_INT0_HPD` to `ADV7511_REG_INT(0)` (a write-1-to-clear register) immediately after `adv7511_power_on()` in `adv7511_bridge_atomic_enable()`. This exactly matches the existing interrupt-clearing pattern used in `adv7511_hpd()` (line ~395) and `adv7511_irq_process()` (line ~453) elsewhere in the same driver.

**Recommendation: This patch looks good to merge.**

---
Generated by Claude Code Patch Reviewer

Claude review: drm/bridge: adv7511: Clear HPD IRQ during atomic_enable()

[Claude Code Review Bot]

Patch Review

**Correctness**: The fix is sound. The `ADV7511_REG_INT(0)` register (address 0x96) uses write-1-to-clear semantics — writing `ADV7511_INT0_HPD` (BIT(7)) clears only the HPD status bit without affecting other interrupt status bits. This is consistent with how the driver already clears interrupts in `adv7511_irq_process()`:

```c
regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
```

and in `adv7511_hpd()`:

```c
regmap_write(adv7511->regmap, ADV7511_REG_INT(0), ADV7511_INT0_HPD);
```

**Placement**: Correct. The clear happens after `adv7511_power_on()`, which powers up the chip and re-enables interrupt generation via `ADV7511_REG_INT_ENABLE(0)`, but does not itself clear any pending status bits. Clearing after power-on ensures the chip is responsive to the register write.

**Scope**: The patch clears only the HPD bit, not other potential stale interrupt bits (EDID_READY, DDC_ERROR, etc.). This is reasonable — HPD is the one specifically reported as causing problems. If other stale interrupts turn out to be an issue, a follow-up could clear all of INT(0) and INT(1), but there's no reason to over-broaden the fix now.

**Minor observation**: The comment is slightly verbose at 4 lines for what is a single write-1-to-clear operation, but it does explain the *why* (stale state across power loss), which is the right kind of comment to include since the reason isn't obvious from the code alone.

**No issues found.** The patch is a clean, minimal, well-targeted fix.

---
Generated by Claude Code Patch Reviewer