* [PATCH v3 1/9] dt-bindings: display: msm-dsi-phy-7nm: document the Milos DSI PHY
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 2/9] dt-bindings: display: msm-dsi-controller-main: document the Milos DSI Controller Luca Weiss
` (8 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss
Document the DSI PHY on the Milos Platform.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
index 966c70d746aa..f397ba3fa84a 100644
--- a/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
@@ -20,6 +20,7 @@ properties:
- qcom,dsi-phy-7nm
- qcom,dsi-phy-7nm-8150
- qcom,kaanapali-dsi-phy-3nm
+ - qcom,milos-dsi-phy-4nm
- qcom,sa8775p-dsi-phy-5nm
- qcom,sar2130p-dsi-phy-5nm
- qcom,sc7280-dsi-phy-7nm
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v3 2/9] dt-bindings: display: msm-dsi-controller-main: document the Milos DSI Controller
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
2026-05-01 7:14 ` [PATCH v3 1/9] dt-bindings: display: msm-dsi-phy-7nm: document the Milos DSI PHY Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 3/9] dt-bindings: display: msm: document the Milos DPU Luca Weiss
` (7 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss
Document the DSI Controller on the Milos Platform.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
index a24fcb914418..dbc0613e427e 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -16,6 +16,7 @@ properties:
- enum:
- qcom,apq8064-dsi-ctrl
- qcom,kaanapali-dsi-ctrl
+ - qcom,milos-dsi-ctrl
- qcom,msm8226-dsi-ctrl
- qcom,msm8916-dsi-ctrl
- qcom,msm8953-dsi-ctrl
@@ -339,6 +340,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,milos-dsi-ctrl
- qcom,msm8998-dsi-ctrl
- qcom,sa8775p-dsi-ctrl
- qcom,sar2130p-dsi-ctrl
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v3 3/9] dt-bindings: display: msm: document the Milos DPU
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
2026-05-01 7:14 ` [PATCH v3 1/9] dt-bindings: display: msm-dsi-phy-7nm: document the Milos DSI PHY Luca Weiss
2026-05-01 7:14 ` [PATCH v3 2/9] dt-bindings: display: msm-dsi-controller-main: document the Milos DSI Controller Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem Luca Weiss
` (6 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss
Document the DPU Display Controller on the Milos Platform.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
index dccac525d202..9da981639ddb 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml
@@ -18,6 +18,7 @@ properties:
- qcom,eliza-dpu
- qcom,glymur-dpu
- qcom,kaanapali-dpu
+ - qcom,milos-dpu
- qcom,sa8775p-dpu
- qcom,sm8650-dpu
- qcom,sm8750-dpu
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v3 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (2 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 3/9] dt-bindings: display: msm: document the Milos DPU Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-03 12:28 ` Krzysztof Kozlowski
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 5/9] soc: qcom: ubwc: Add config for Milos Luca Weiss
` (5 subsequent siblings)
9 siblings, 2 replies; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss
Document the Mobile Display Subsystem (MDSS) on the Milos SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../bindings/display/msm/qcom,milos-mdss.yaml | 286 +++++++++++++++++++++
1 file changed, 286 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml
new file mode 100644
index 000000000000..7010ffa0ae35
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml
@@ -0,0 +1,286 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Milos Display MDSS
+
+maintainers:
+ - Luca Weiss <luca.weiss@fairphone.com>
+
+description:
+ Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
+ DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,milos-mdss
+
+ clocks:
+ items:
+ - description: Display AHB
+ - description: Display hf AXI
+ - description: Display core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ items:
+ - description: Interconnect path from mdp0 port to the data bus
+ - description: Interconnect path from CPU to the reg bus
+
+ interconnect-names:
+ items:
+ - const: mdp0-mem
+ - const: cpu-cfg
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,milos-dpu
+
+ "^displayport-controller@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,milos-dp
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ contains:
+ const: qcom,milos-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ additionalProperties: true
+ properties:
+ compatible:
+ const: qcom,milos-dsi-phy-4nm
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
+ #include <dt-bindings/clock/qcom,milos-dispcc.h>
+ #include <dt-bindings/clock/qcom,milos-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,milos-rpmh.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ display-subsystem@ae00000 {
+ compatible = "qcom,milos-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,milos-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-342000000 {
+ opp-hz = /bits/ 64 <342000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-402000000 {
+ opp-hz = /bits/ 64 <402000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-535000000 {
+ opp-hz = /bits/ 64 <535000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ dsi@ae94000 {
+ compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x1000>;
+ reg-names = "dsi_ctrl";
+
+ interrupts-extended = <&mdss 4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae95000 {
+ compatible = "qcom,milos-dsi-phy-4nm";
+ reg = <0x0ae95000 0x200>,
+ <0x0ae95200 0x300>,
+ <0x0ae95500 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
+ };
+...
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v3 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem
2026-05-01 7:14 ` [PATCH v3 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem Luca Weiss
@ 2026-05-03 12:28 ` Krzysztof Kozlowski
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
1 sibling, 0 replies; 21+ messages in thread
From: Krzysztof Kozlowski @ 2026-05-03 12:28 UTC (permalink / raw)
To: Luca Weiss
Cc: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich, ~postmarketos/upstreaming, phone-devel,
linux-arm-msm, linux-kernel, dri-devel, freedreno, devicetree
On Fri, May 01, 2026 at 09:14:46AM +0200, Luca Weiss wrote:
> Document the Mobile Display Subsystem (MDSS) on the Milos SoC.
>
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
> .../bindings/display/msm/qcom,milos-mdss.yaml | 286 +++++++++++++++++++++
> 1 file changed, 286 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 21+ messages in thread
* Claude review: dt-bindings: display: msm: document the Milos Mobile Display Subsystem
2026-05-01 7:14 ` [PATCH v3 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem Luca Weiss
2026-05-03 12:28 ` Krzysztof Kozlowski
@ 2026-05-04 23:35 ` Claude Code Review Bot
1 sibling, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Patch Review
New YAML binding file for the Milos MDSS. The structure follows the established pattern from similar SoCs (sm8650-mdss, etc.), referencing the common `mdss-common.yaml` schema. The `patternProperties` section correctly constrains child nodes (display-controller, displayport-controller, dsi, phy) to their respective Milos-specific compatibles. The DSI node uses `contains` for matching (fixed in v3).
The example is comprehensive and includes the full MDSS, DPU, DSI controller, and DSI PHY sub-nodes with proper clock/interconnect/power-domain references. Notably includes a `displayport-controller` pattern even though DP support isn't added in this series -- that's fine for forward compatibility.
**Note**: This patch does not carry an Ack from a DT maintainer (unlike patches 1-3). Not blocking, but the DT maintainers may want to review the new file.
No code issues.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 5/9] soc: qcom: ubwc: Add config for Milos
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (3 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 6/9] drm/msm/dsi: add support for DSI-PHY on Milos Luca Weiss
` (4 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss,
Konrad Dybcio, Dmitry Baryshkov
Describe the Universal Bandwidth Compression (UBWC) configuration
for the Milos SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/soc/qcom/ubwc_config.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c
index 3fe47d8f0f63..1551f270afce 100644
--- a/drivers/soc/qcom/ubwc_config.c
+++ b/drivers/soc/qcom/ubwc_config.c
@@ -37,6 +37,17 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = {
.macrotile_mode = true,
};
+static const struct qcom_ubwc_cfg_data milos_data = {
+ .ubwc_enc_version = UBWC_4_0,
+ .ubwc_dec_version = UBWC_4_0,
+ .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
+ UBWC_SWIZZLE_ENABLE_LVL3,
+ .ubwc_bank_spread = true,
+ /* TODO: highest_bank_bit = 14 for LP_DDR4 */
+ .highest_bank_bit = 15,
+ .macrotile_mode = true,
+};
+
static const struct qcom_ubwc_cfg_data msm8937_data = {
.ubwc_enc_version = UBWC_1_0,
.ubwc_dec_version = UBWC_1_0,
@@ -247,6 +258,7 @@ static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
{ .compatible = "qcom,kaanapali", .data = &kaanapali_data, },
{ .compatible = "qcom,glymur", .data = &glymur_data},
{ .compatible = "qcom,mahua", .data = &glymur_data },
+ { .compatible = "qcom,milos", .data = &milos_data },
{ .compatible = "qcom,msm8226", .data = &no_ubwc_data },
{ .compatible = "qcom,msm8916", .data = &no_ubwc_data },
{ .compatible = "qcom,msm8917", .data = &no_ubwc_data },
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Claude review: soc: qcom: ubwc: Add config for Milos
2026-05-01 7:14 ` [PATCH v3 5/9] soc: qcom: ubwc: Add config for Milos Luca Weiss
@ 2026-05-04 23:35 ` Claude Code Review Bot
0 siblings, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Patch Review
Adds UBWC configuration for Milos: UBWC 4.0 encode/decode, level 2+3 swizzle, bank spread enabled, highest_bank_bit=15, macrotile mode.
```c
/* TODO: highest_bank_bit = 14 for LP_DDR4 */
.highest_bank_bit = 15,
```
This TODO is worth tracking. If any Milos-based device ships with LPDDR4 instead of LPDDR5, this will need runtime detection or a separate config. For now this is fine since the known devices (Fairphone 6, Nothing Phone 3a) use LPDDR5.
Has Reviewed-by from both Konrad and Dmitry. No blocking issues.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 6/9] drm/msm/dsi: add support for DSI-PHY on Milos
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (4 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 5/9] soc: qcom: ubwc: Add config for Milos Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 7/9] drm/msm: mdss: Add Milos support Luca Weiss
` (3 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss,
Dmitry Baryshkov
Add DSI PHY support for the Milos platform.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++
3 files changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index c59375aaae19..1fb3899b88bf 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -571,6 +571,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
.data = &dsi_phy_5nm_8350_cfgs },
{ .compatible = "qcom,sm8450-dsi-phy-5nm",
.data = &dsi_phy_5nm_8450_cfgs },
+ { .compatible = "qcom,milos-dsi-phy-4nm",
+ .data = &dsi_phy_4nm_milos_cfgs },
{ .compatible = "qcom,sm8550-dsi-phy-4nm",
.data = &dsi_phy_4nm_8550_cfgs },
{ .compatible = "qcom,sm8650-dsi-phy-4nm",
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index c01784ca38ed..21a59d66e8dc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -61,6 +61,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs;
+extern const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs;
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 8f4b03713f25..984a66085dfb 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -1436,6 +1436,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs = {
.quirks = DSI_PHY_7NM_QUIRK_V5_2,
};
+const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs = {
+ .has_phy_lane = true,
+ .regulator_data = dsi_phy_7nm_98000uA_regulators,
+ .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators),
+ .ops = {
+ .enable = dsi_7nm_phy_enable,
+ .disable = dsi_7nm_phy_disable,
+ .pll_init = dsi_pll_7nm_init,
+ .save_pll_state = dsi_7nm_pll_save_state,
+ .restore_pll_state = dsi_7nm_pll_restore_state,
+ .set_continuous_clock = dsi_7nm_set_continuous_clock,
+ },
+ .min_pll_rate = 600000000UL,
+#ifdef CONFIG_64BIT
+ .max_pll_rate = 5000000000UL,
+#else
+ .max_pll_rate = ULONG_MAX,
+#endif
+ .io_start = { 0xae95000 },
+ .num_dsi_phy = 1,
+ .quirks = DSI_PHY_7NM_QUIRK_V5_2,
+};
+
const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
.has_phy_lane = true,
.regulator_data = dsi_phy_7nm_98400uA_regulators,
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Claude review: drm/msm/dsi: add support for DSI-PHY on Milos
2026-05-01 7:14 ` [PATCH v3 6/9] drm/msm/dsi: add support for DSI-PHY on Milos Luca Weiss
@ 2026-05-04 23:35 ` Claude Code Review Bot
0 siblings, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Patch Review
Adds the DSI PHY configuration for Milos. The config closely matches `dsi_phy_4nm_8650_cfgs` (SM8650) with two intentional differences:
1. `.num_dsi_phy = 1` (vs 2 on SM8650) -- correct, Milos has a single DSI interface
2. `.io_start = { 0xae95000 }` -- only one PHY address, matching the DTS
Uses `dsi_phy_7nm_98000uA_regulators` (same as SM8650) and `DSI_PHY_7NM_QUIRK_V5_2`. All looks correct.
Has Reviewed-by from Dmitry. No issues.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 7/9] drm/msm: mdss: Add Milos support
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (5 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 6/9] drm/msm/dsi: add support for DSI-PHY on Milos Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 8/9] drm/msm/dpu: " Luca Weiss
` (2 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss,
Konrad Dybcio, Dmitry Baryshkov
Add support for MDSS on Milos.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
drivers/gpu/drm/msm/msm_mdss.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c
index 90c3fa0681a0..754ceef38717 100644
--- a/drivers/gpu/drm/msm/msm_mdss.c
+++ b/drivers/gpu/drm/msm/msm_mdss.c
@@ -550,6 +550,10 @@ static void mdss_remove(struct platform_device *pdev)
msm_mdss_destroy(mdss);
}
+static const struct msm_mdss_data data_14k = {
+ .reg_bus_bw = 14000,
+};
+
static const struct msm_mdss_data data_57k = {
.reg_bus_bw = 57000,
};
@@ -571,6 +575,7 @@ static const struct of_device_id mdss_dt_match[] = {
{ .compatible = "qcom,eliza-mdss", .data = &data_57k },
{ .compatible = "qcom,glymur-mdss", .data = &data_57k },
{ .compatible = "qcom,kaanapali-mdss", .data = &data_57k },
+ { .compatible = "qcom,milos-mdss", .data = &data_14k },
{ .compatible = "qcom,msm8998-mdss", .data = &data_76k8 },
{ .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 },
{ .compatible = "qcom,qcs8300-mdss", .data = &data_74k },
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Claude review: drm/msm: mdss: Add Milos support
2026-05-01 7:14 ` [PATCH v3 7/9] drm/msm: mdss: Add Milos support Luca Weiss
@ 2026-05-04 23:35 ` Claude Code Review Bot
0 siblings, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Patch Review
Adds a new `data_14k` struct with `reg_bus_bw = 14000` and maps it to `qcom,milos-mdss`. This is the lowest reg bus bandwidth value in the entire table (other recent SoCs use 57000 for kaanapali/eliza/glymur, 74000-76800 for older ones). This makes sense for a mid-range SoC with a smaller display pipe configuration.
```c
static const struct msm_mdss_data data_14k = {
.reg_bus_bw = 14000,
};
```
Has Reviewed-by from both Konrad and Dmitry. No issues.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 8/9] drm/msm/dpu: Add Milos support
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (6 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 7/9] drm/msm: mdss: Add Milos support Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-01 7:14 ` [PATCH v3 9/9] arm64: dts: qcom: milos: Add display (MDSS) Luca Weiss
2026-05-04 23:35 ` Claude review: MDSS / DPU bringup for Milos Claude Code Review Bot
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss
Add definitions for the display hardware used on the Qualcomm Milos
platform.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h | 279 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 310 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
new file mode 100644
index 000000000000..1aa8aea4e352
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2026, Luca Weiss <luca.weiss@fairphone.com>
+ */
+
+#ifndef _DPU_10_2_MILOS_H
+#define _DPU_10_2_MILOS_H
+
+static const struct dpu_caps milos_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 8192,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg milos_mdp = {
+ .name = "top_0",
+ .base = 0, .len = 0x494,
+ .clk_ctrls = {
+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg milos_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ }, {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ }, {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ }, {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x1000,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg milos_sspp[] = {
+ {
+ .name = "sspp_0", .id = SSPP_VIG0,
+ .base = 0x4000, .len = 0x344,
+ .features = VIG_SDM845_MASK_SDMA,
+ .sblk = &dpu_vig_sblk_qseed3_3_3,
+ .xin_id = 0,
+ .type = SSPP_TYPE_VIG,
+ }, {
+ .name = "sspp_8", .id = SSPP_DMA0,
+ .base = 0x24000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 1,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_9", .id = SSPP_DMA1,
+ .base = 0x26000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 5,
+ .type = SSPP_TYPE_DMA,
+ }, {
+ .name = "sspp_10", .id = SSPP_DMA2,
+ .base = 0x28000, .len = 0x344,
+ .features = DMA_SDM845_MASK_SDMA,
+ .sblk = &dpu_dma_sblk,
+ .xin_id = 9,
+ .type = SSPP_TYPE_DMA,
+ },
+};
+
+static const struct dpu_lm_cfg milos_lm[] = {
+ {
+ .name = "lm_0", .id = LM_0,
+ .base = 0x44000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .pingpong = PINGPONG_0,
+ .dspp = DSPP_0,
+ }, {
+ .name = "lm_2", .id = LM_2,
+ .base = 0x46000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_3,
+ .pingpong = PINGPONG_2,
+ }, {
+ .name = "lm_3", .id = LM_3,
+ .base = 0x47000, .len = 0x400,
+ .features = MIXER_MSM8998_MASK,
+ .sblk = &sdm845_lm_sblk,
+ .lm_pair = LM_2,
+ .pingpong = PINGPONG_3,
+ },
+};
+
+static const struct dpu_dspp_cfg milos_dspp[] = {
+ {
+ .name = "dspp_0", .id = DSPP_0,
+ .base = 0x54000, .len = 0x1800,
+ .sblk = &sdm845_dspp_sblk,
+ },
+};
+
+static const struct dpu_pingpong_cfg milos_pp[] = {
+ {
+ .name = "pingpong_0", .id = PINGPONG_0,
+ .base = 0x69000, .len = 0,
+ .sblk = &sc7280_pp_sblk,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ }, {
+ .name = "pingpong_2", .id = PINGPONG_2,
+ .base = 0x6b000, .len = 0,
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+ }, {
+ .name = "pingpong_3", .id = PINGPONG_3,
+ .base = 0x6c000, .len = 0,
+ .sblk = &sc7280_pp_sblk,
+ .merge_3d = MERGE_3D_1,
+ .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+ }, {
+ .name = "pingpong_cwb_0", .id = PINGPONG_CWB_0,
+ .base = 0x66000, .len = 0,
+ .sblk = &sc7280_pp_sblk,
+ },
+};
+
+static const struct dpu_merge_3d_cfg milos_merge_3d[] = {
+ {
+ .name = "merge_3d_1", .id = MERGE_3D_1,
+ .base = 0x4f000, .len = 0x8,
+ },
+};
+
+/*
+ * NOTE: Each display compression engine (DCE) contains dual hard
+ * slice DSC encoders so both share same base address but with
+ * its own different sub block address.
+ */
+static const struct dpu_dsc_cfg milos_dsc[] = {
+ {
+ .name = "dce_0_0", .id = DSC_0,
+ .base = 0x80000, .len = 0x6,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &milos_dsc_sblk_0,
+ }, {
+ .name = "dce_0_1", .id = DSC_1,
+ .base = 0x80000, .len = 0x6,
+ .features = BIT(DPU_DSC_NATIVE_42x_EN),
+ .sblk = &milos_dsc_sblk_1,
+ },
+};
+
+static const struct dpu_wb_cfg milos_wb[] = {
+ {
+ .name = "wb_2", .id = WB_2,
+ .base = 0x65000, .len = 0x2c8,
+ .features = WB_SDM845_MASK,
+ .format_list = wb2_formats_rgb_yuv,
+ .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
+ .xin_id = 6,
+ .maxlinewidth = 4096,
+ .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
+ },
+};
+
+static const struct dpu_cwb_cfg milos_cwb[] = {
+ {
+ .name = "cwb_0", .id = CWB_0,
+ .base = 0x66200, .len = 0x8,
+ },
+};
+
+static const struct dpu_intf_cfg milos_intf[] = {
+ {
+ .name = "intf_0", .id = INTF_0,
+ .base = 0x34000, .len = 0x300,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
+ }, {
+ .name = "intf_1", .id = INTF_1,
+ .base = 0x35000, .len = 0x300,
+ .type = INTF_DSI,
+ .controller_id = MSM_DSI_CONTROLLER_0,
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
+ }, {
+ .name = "intf_3", .id = INTF_3,
+ .base = 0x37000, .len = 0x300,
+ .type = INTF_DP,
+ .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */
+ .prog_fetch_lines_worst_case = 24,
+ .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
+ .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+ },
+};
+
+static const struct dpu_perf_cfg milos_perf_data = {
+ .max_bw_low = 7100000,
+ .max_bw_high = 9800000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 40,
+ /* FIXME: lut tables */
+ .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+ .safe_lut_tbl = {0xff00, 0xfff0, 0x0fff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+ .entries = sc7180_qos_linear
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+ .entries = sc7180_qos_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ /* TODO: macrotile-qseed is different from macrotile */
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_version milos_mdss_ver = {
+ .core_major_ver = 10,
+ .core_minor_ver = 2,
+};
+
+const struct dpu_mdss_cfg dpu_milos_cfg = {
+ .mdss_ver = &milos_mdss_ver,
+ .caps = &milos_dpu_caps,
+ .mdp = &milos_mdp,
+ .cdm = &dpu_cdm_5_x,
+ .ctl_count = ARRAY_SIZE(milos_ctl),
+ .ctl = milos_ctl,
+ .sspp_count = ARRAY_SIZE(milos_sspp),
+ .sspp = milos_sspp,
+ .mixer_count = ARRAY_SIZE(milos_lm),
+ .mixer = milos_lm,
+ .dspp_count = ARRAY_SIZE(milos_dspp),
+ .dspp = milos_dspp,
+ .pingpong_count = ARRAY_SIZE(milos_pp),
+ .pingpong = milos_pp,
+ .dsc_count = ARRAY_SIZE(milos_dsc),
+ .dsc = milos_dsc,
+ .merge_3d_count = ARRAY_SIZE(milos_merge_3d),
+ .merge_3d = milos_merge_3d,
+ .wb_count = ARRAY_SIZE(milos_wb),
+ .wb = milos_wb,
+ .cwb_count = ARRAY_SIZE(milos_cwb),
+ .cwb = milos_cwb,
+ .intf_count = ARRAY_SIZE(milos_intf),
+ .intf = milos_intf,
+ .vbif = &milos_vbif,
+ .perf = &milos_perf_data,
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index bb4fd5fa4b22..2e10add84fd7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -454,6 +454,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = {
.ctl = {.name = "ctl", .base = 0xF80, .len = 0x10},
};
+static const struct dpu_dsc_sub_blks milos_dsc_sblk_0 = {
+ .enc = {.name = "enc", .base = 0x100, .len = 0x100},
+ .ctl = {.name = "ctl", .base = 0xF00, .len = 0x80},
+};
+
+static const struct dpu_dsc_sub_blks milos_dsc_sblk_1 = {
+ .enc = {.name = "enc", .base = 0x200, .len = 0x100},
+ .ctl = {.name = "ctl", .base = 0xF80, .len = 0x80},
+};
+
static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 = {
.enc = {.name = "enc", .base = 0x100, .len = 0x100},
.ctl = {.name = "ctl", .base = 0xF00, .len = 0x24},
@@ -513,6 +523,23 @@ static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
},
};
+static const struct dpu_vbif_cfg milos_vbif = {
+ .len = 0x1074,
+ .features = BIT(DPU_VBIF_QOS_REMAP),
+ .xin_halt_timeout = 0x4000,
+ .qos_rp_remap_size = 0x40,
+ .qos_rt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
+ .priority_lvl = sdm845_rt_pri_lvl,
+ },
+ .qos_nrt_tbl = {
+ .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
+ .priority_lvl = sdm845_nrt_pri_lvl,
+ },
+ .memtype_count = 16,
+ .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
+};
+
static const struct dpu_vbif_cfg msm8996_vbif = {
.len = 0x1040,
.default_ot_rd_limit = 32,
@@ -754,6 +781,8 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_9_2_x1e80100.h"
#include "catalog/dpu_10_0_sm8650.h"
+#include "catalog/dpu_10_2_milos.h"
+
#include "catalog/dpu_12_0_sm8750.h"
#include "catalog/dpu_12_2_glymur.h"
#include "catalog/dpu_12_4_eliza.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index ba04ac24d5a9..f45faf87333e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -766,6 +766,7 @@ struct dpu_mdss_cfg {
extern const struct dpu_mdss_cfg dpu_eliza_cfg;
extern const struct dpu_mdss_cfg dpu_glymur_cfg;
extern const struct dpu_mdss_cfg dpu_kaanapali_cfg;
+extern const struct dpu_mdss_cfg dpu_milos_cfg;
extern const struct dpu_mdss_cfg dpu_msm8917_cfg;
extern const struct dpu_mdss_cfg dpu_msm8937_cfg;
extern const struct dpu_mdss_cfg dpu_msm8953_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 35f7af4743d7..7c37bd51f934 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1483,6 +1483,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,eliza-dpu", .data = &dpu_eliza_cfg, },
{ .compatible = "qcom,glymur-dpu", .data = &dpu_glymur_cfg, },
{ .compatible = "qcom,kaanapali-dpu", .data = &dpu_kaanapali_cfg, },
+ { .compatible = "qcom,milos-dpu", .data = &dpu_milos_cfg, },
{ .compatible = "qcom,msm8917-mdp5", .data = &dpu_msm8917_cfg, },
{ .compatible = "qcom,msm8937-mdp5", .data = &dpu_msm8937_cfg, },
{ .compatible = "qcom,msm8953-mdp5", .data = &dpu_msm8953_cfg, },
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Claude review: drm/msm/dpu: Add Milos support
2026-05-01 7:14 ` [PATCH v3 8/9] drm/msm/dpu: " Luca Weiss
@ 2026-05-04 23:35 ` Claude Code Review Bot
0 siblings, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Patch Review
This is the largest and most complex patch. Creates the DPU 10.2 catalog for Milos. Several observations:
**DSC sub-blocks -- unusual ctl register length:**
```c
static const struct dpu_dsc_sub_blks milos_dsc_sblk_0 = {
.enc = {.name = "enc", .base = 0x100, .len = 0x100},
.ctl = {.name = "ctl", .base = 0xF00, .len = 0x80},
};
```
The `.ctl.len = 0x80` (128 bytes) is significantly larger than any other platform: the default is `0x10`, SM8750 uses `0x24`. The `.enc.len = 0x100` matches SM8750. Is the 0x80 ctl length verified from the hardware documentation? It's not wrong per se, but it stands out as an outlier. All this register length does is gate how much of the register space the driver will consider "owned" by this sub-block, so over-sizing is usually harmless, but worth confirming.
**VBIF configuration:**
```c
static const struct dpu_vbif_cfg milos_vbif = {
...
.qos_rt_tbl = {
.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
.priority_lvl = sdm845_rt_pri_lvl,
},
```
This creates a new VBIF config that is structurally identical to `sm8650_vbif` but uses `sdm845_rt_pri_lvl` (`{3, 3, 4, 4, 5, 5, 6, 6}`) instead of `sm8650_rt_pri_lvl` (`{4, 4, 5, 5, 5, 5, 5, 6}`). Every DPU 9.0+ SoC in-tree uses `sm8650_vbif` or `sm8550_vbif` (both with their own higher priority levels). Using the SDM845 RT priorities for a DPU 10.2 SoC is a deliberate choice -- presumably reflecting the mid-range tier having fewer AXI paths and different QoS requirements. This seems fine given it's tested on hardware.
**Performance data TODO/FIXME markers:**
```c
/* FIXME: lut tables */
.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
...
/* TODO: macrotile-qseed is different from macrotile */
```
These indicate the perf tuning is not finalized. The QoS LUT tables reference `sc7180_qos_*` which matches what SM8650 does (so this is the established pattern, not a concern). The danger/safe LUT values are placeholder-like; they should be verified against the hardware programming guide when available.
**Hardware topology -- scaled down from SM8650:**
- 1 VIG (vs 4 on SM8650), 3 DMA (vs 6), 3 LMs (vs 6), 1 DSPP (vs 4), 4 CTLs (vs 6)
- LM_0 stands alone with DSPP_0, LM_2+LM_3 are paired for 3D merge but without DSPPs
- Single DSI + DP interface (vs dual on SM8650)
This is a reasonable cut-down for a mid-range SoC focused on single-panel use.
**Missing Reviewed-by tags**: This is the only driver patch without any Reviewed-by, which is worth noting given it's the most complex patch in the series.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v3 9/9] arm64: dts: qcom: milos: Add display (MDSS)
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (7 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 8/9] drm/msm/dpu: " Luca Weiss
@ 2026-05-01 7:14 ` Luca Weiss
2026-05-04 23:35 ` Claude review: " Claude Code Review Bot
2026-05-04 23:35 ` Claude review: MDSS / DPU bringup for Milos Claude Code Review Bot
9 siblings, 1 reply; 21+ messages in thread
From: Luca Weiss @ 2026-05-01 7:14 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Clark, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Sean Paul, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Jonathan Marek, Krishna Manikandan, Neil Armstrong,
Alexander Koskovich
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-kernel, dri-devel, freedreno, devicetree, Luca Weiss,
Konrad Dybcio
Add device nodes for display: MDSS, DPU, DSI and DSI PHY.
DisplayPort is not added for now.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 211 +++++++++++++++++++++++++++++++++++-
1 file changed, 209 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 4a64a98a434b..1a9b72d61688 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
*/
+#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,milos-camcc.h>
#include <dt-bindings/clock/qcom,milos-dispcc.h>
#include <dt-bindings/clock/qcom,milos-gcc.h>
@@ -1928,6 +1929,212 @@ camcc: clock-controller@adb0000 {
#power-domain-cells = <1>;
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,milos-mdss";
+ reg = <0x0 0x0ae00000 0x0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,milos-dpu";
+ reg = <0x0 0x0ae01000 0x0 0x8f000>,
+ <0x0 0x0aeb0000 0x0 0x3000>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&mdss_dsi0_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-342000000 {
+ opp-hz = /bits/ 64 <342000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-402000000 {
+ opp-hz = /bits/ 64 <402000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-535000000 {
+ opp-hz = /bits/ 64 <535000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ };
+ };
+ };
+
+ mdss_dsi0: dsi@ae94000 {
+ compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x0 0x0ae94000 0x0 0x1000>;
+ reg-names = "dsi_ctrl";
+
+ interrupts-extended = <&mdss 4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+
+ operating-points-v2 = <&mdss_dsi_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_CX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dsi0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dsi_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-187500000 {
+ opp-hz = /bits/ 64 <187500000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-358000000 {
+ opp-hz = /bits/ 64 <358000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@ae95000 {
+ compatible = "qcom,milos-dsi-phy-4nm";
+ reg = <0x0 0x0ae95000 0x0 0x200>,
+ <0x0 0x0ae95200 0x0 0x300>,
+ <0x0 0x0ae95500 0x0 0x400>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface",
+ "ref";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+ };
+
dispcc: clock-controller@af00000 {
compatible = "qcom,milos-dispcc";
reg = <0x0 0x0af00000 0x0 0x20000>;
@@ -1936,8 +2143,8 @@ dispcc: clock-controller@af00000 {
<&sleep_clk>,
<&gcc GCC_DISP_AHB_CLK>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
- <0>, /* dsi0_phy_pll_out_byteclk */
- <0>, /* dsi0_phy_pll_out_dsiclk */
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<0>, /* dp0_phy_pll_link_clk */
<0>; /* dp0_phy_pll_vco_div_clk */
--
2.54.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* Claude review: arm64: dts: qcom: milos: Add display (MDSS)
2026-05-01 7:14 ` [PATCH v3 9/9] arm64: dts: qcom: milos: Add display (MDSS) Luca Weiss
@ 2026-05-04 23:35 ` Claude Code Review Bot
0 siblings, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Patch Review
Adds the complete MDSS device tree nodes (MDSS, DPU, DSI controller, DSI PHY) to milos.dtsi, and wires up the dispcc clock controller to use the DSI PHY clocks instead of the `<0>` placeholders.
The DTS matches the DT binding example from Patch 4 almost exactly (with expected differences like `#address-cells = <2>` in the actual DTS vs `<1>` in the binding example, and `status = "disabled"` in the actual nodes).
```diff
- <0>, /* dsi0_phy_pll_out_byteclk */
- <0>, /* dsi0_phy_pll_out_dsiclk */
+ <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
```
This correctly replaces the stub clock references in the display clock controller with the actual DSI PHY PLL outputs. The `dt-bindings/clock/qcom,dsi-phy-28nm.h` include is added for `DSI_BYTE_PLL_CLK` and `DSI_PIXEL_PLL_CLK` constants.
All nodes are `status = "disabled"` by default, to be enabled by board-level DTS files. Has Reviewed-by from Konrad. No issues.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread
* Claude review: MDSS / DPU bringup for Milos
2026-05-01 7:14 [PATCH v3 0/9] MDSS / DPU bringup for Milos Luca Weiss
` (8 preceding siblings ...)
2026-05-01 7:14 ` [PATCH v3 9/9] arm64: dts: qcom: milos: Add display (MDSS) Luca Weiss
@ 2026-05-04 23:35 ` Claude Code Review Bot
9 siblings, 0 replies; 21+ messages in thread
From: Claude Code Review Bot @ 2026-05-04 23:35 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: MDSS / DPU bringup for Milos
Author: Luca Weiss <luca.weiss@fairphone.com>
Patches: 11
Reviewed: 2026-05-05T09:35:33.670003
---
This is a well-structured 9-patch series adding display (MDSS/DPU/DSI) support for the Qualcomm Milos SoC (SM7635), a mid-range platform used in the Fairphone Gen. 6. The series follows the established patterns for Qualcomm display bringup: DT bindings first, then UBWC config, DSI PHY, MDSS, DPU catalog, and finally the DTS nodes.
The series is at v3 with good review coverage -- patches 1-3 have DT Acks from Rob Herring, patches 5 and 7 have Reviewed-by from both Konrad Dybcio and Dmitry Baryshkov, patch 6 has Reviewed-by from Dmitry, and patch 9 has Reviewed-by from Konrad. The author reports it's tested on real hardware (Fairphone Gen. 6) and confirmed working on Nothing Phone (3a).
The main area deserving closer scrutiny is Patch 8 (DPU catalog), which has the most complexity and carries a few TODO/FIXME markers indicating the perf tuning is not fully finalized. This is typical for initial bringup but should be tracked. The DSC sub-block register sizes are notably different from all existing platforms and warrant verification.
Overall: series looks ready for merge, with a couple of points to confirm below.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 21+ messages in thread