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From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/panel: Enable DSC for Visionox VTDR6130 panel
Date: Fri, 05 Jun 2026 06:24:33 +1000	[thread overview]
Message-ID: <review-patch1-20260604-topic-sm8x50-vtdr6130-dsc-v1-1-09bcd1dff1fb@linaro.org> (raw)
In-Reply-To: <20260604-topic-sm8x50-vtdr6130-dsc-v1-1-09bcd1dff1fb@linaro.org>

Patch Review

**Author:** Jun Nie, signed-off by Neil Armstrong.

This patch adds structured DSC configuration and sends the PPS via the standard MIPI DCS Picture Parameter Set command.

**DSC configuration (probe):**
```c
+	ctx->dsc.dsc_version_major = 0x1;
+	ctx->dsc.dsc_version_minor = 0x2;
+	ctx->dsc.slice_height = 40;
+	ctx->dsc.slice_width = 540;
+	ctx->dsc.slice_count = 2;
+	ctx->dsc.bits_per_component = 8;
+	ctx->dsc.bits_per_pixel = 8 << 4;
+	ctx->dsc.block_pred_enable = true;
+
+	dsi->dsc = &ctx->dsc;
```

These parameters are consistent with the existing hardcoded PPS blob in the 0x70 vendor register (which decodes to: DSC 1.2, pic_height=2400, pic_width=1080, slice_height=40, slice_width=540). The `bits_per_pixel = 8 << 4` (128, i.e. 8.0 bpp with 4 fractional bits) matches the pattern used across all other panel drivers. The remaining DSC parameters (RC model, initial offset, etc.) are populated by the MSM DSI host driver via `dsi_populate_dsc_params()` when it sees `dsi->dsc` is set.

**DSC enable command:**
```c
+	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x01);
```

DCS command 0x03 with value 0x01 enables compression mode on the panel. This is placed correctly at the top of the `_on()` function before other initialization — good.

**PPS transmission:**
```c
+	drm_dsc_pps_payload_pack(&pps, dsi->dsc);
+	mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps);
```

Placed after display-on and the 20ms delay. This follows the pattern of other DSC-enabled panel drivers (`panel-visionox-r66451`, `panel-lg-sw43408`, etc.).

**Minor observation (non-blocking):** The existing driver already has a hardcoded PPS-like blob written to vendor register 0x70 (line 64 in the current source). That blob's decoded parameters (DSC 1.2, slice 40x540, 1080x2400) match the new structured DSC config exactly. It would be worth confirming that both the vendor register write and the standard MIPI PPS are needed — but this is common for Qualcomm-reference panels and is almost certainly correct.

**Verdict:** Looks correct. No issues.

---
Generated by Claude Code Patch Reviewer

  parent reply	other threads:[~2026-06-04 20:24 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-04 12:41 [PATCH 0/2] drm/panel: couple of visionox vtdr6140 driver enhancements Neil Armstrong
2026-06-04 12:41 ` [PATCH 1/2] drm/panel: Enable DSC for Visionox VTDR6130 panel Neil Armstrong
2026-06-04 13:03   ` sashiko-bot
2026-06-04 14:42     ` Neil Armstrong
2026-06-04 20:24   ` Claude Code Review Bot [this message]
2026-06-04 12:41 ` [PATCH 2/2] drm/panel: visionox-vtdr6130: switch to devm panel calls and drop remove Neil Armstrong
2026-06-04 20:24   ` Claude review: " Claude Code Review Bot
2026-06-04 20:24 ` Claude review: drm/panel: couple of visionox vtdr6140 driver enhancements Claude Code Review Bot

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