[PATCH 0/5] drm/rcar-du: Add support for DSI pipelines with DSC

[PATCH 0/5] drm/rcar-du: Add support for DSI pipelines with DSC

[Tomi Valkeinen]

Some DSI pipelines have DSC (Display Stream Compression) IP block
between the DU and the DSI. Even if DSC is not needed, the IP must be
enabled for the DSI output to work.

This series adds a basic DSC driver, so that the DSC IP gets enabled in
bypass mode. This enables DisplayPort output on Sparrow Hawk board, as
the DP output comes from DSI and sn65dsi86 bridge.

Original series from Marek.

Note: I see that not every run of kms++'s kmstest gives me a picture on
my monitor. Sometimes the monitor seems to be trying to repeatedly sync,
but fails, and the screen stays black. However, I see this same issue on
WhiteHawk, which uses DSI0 pipeline, without DSC, so I think that is a
separate issue.

 Tomi

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
Marek Vasut (4):
      clk: renesas: r8a779g0: Add DSC clock
      dt-bindings: display: bridge: Document Renesas R-Car V4H DSC bindings
      drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver
      arm64: dts: renesas: Add Renesas R-Car V4H DSC

Tomi Valkeinen (1):
      drm/rcar-du: dsi: Support DSC in the pipeline

 .../bindings/display/bridge/renesas,dsc.yaml       |  96 ++++++++++++
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi          |  31 +++-
 .../boot/dts/renesas/r8a779g3-sparrow-hawk.dts     |   5 +
 drivers/clk/renesas/r8a779g0-cpg-mssr.c            |   1 +
 drivers/gpu/drm/renesas/rcar-du/Kconfig            |  13 ++
 drivers/gpu/drm/renesas/rcar-du/Makefile           |   1 +
 drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c         | 163 +++++++++++++++++++++
 drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c    |  36 ++++-
 8 files changed, 343 insertions(+), 3 deletions(-)
---
base-commit: 028ef9c96e96197026887c0f092424679298aae8
change-id: 20260514-rcar-du-dsc-45bcf0c2fe86

Best regards,
-- 
Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>

[PATCH 1/5] clk: renesas: r8a779g0: Add DSC clock

[Tomi Valkeinen]

From: Marek Vasut <marek.vasut+renesas@mailbox.org>

Add the DSC module clock for Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
 drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 015b9773cc55..54ba76ff5ab0 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -245,6 +245,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
 	DEF_MOD("fcpvx0",	1100,	R8A779G0_CLK_S0D1_VIO),
 	DEF_MOD("fcpvx1",	1101,	R8A779G0_CLK_S0D1_VIO),
 	DEF_MOD("tsn",		2723,	R8A779G0_CLK_S0D4_HSC),
+	DEF_MOD("dsc",		2819,	R8A779G0_CLK_VIOBUSD2),
 	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),
 	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),
 };

-- 
2.43.0

[PATCH 2/5] dt-bindings: display: bridge: Document Renesas R-Car V4H DSC bindings

[Tomi Valkeinen]

From: Marek Vasut <marek.vasut+renesas@mailbox.org>

The Renesas DSC Display Stream Compression is a bridge embedded in the
Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
8k or 400 Mpixel/s .

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[tomi.valkeinen: fix the example]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
 .../bindings/display/bridge/renesas,dsc.yaml       | 96 ++++++++++++++++++++++
 1 file changed, 96 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsc.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsc.yaml
new file mode 100644
index 000000000000..91245beb67d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsc.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/renesas,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car DSC Display Stream Compression
+
+maintainers:
+  - Marek Vasut <marek.vasut+renesas@mailbox.org>
+
+description: |
+  This binding describes the VESA DSC Display Stream Compression encoder
+  embedded in the Renesas R-Car V4H SoC. The encoder supports all DSC1.1
+  encoding mechanisms, configurable bits-per-pixel, resolution up to 8k.
+
+properties:
+  compatible:
+    const: renesas,r8a779g0-dsc
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: R-Car DU input port
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description: R-Car DSI output port
+
+    required:
+      - port@0
+      - port@1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - interrupts
+  - power-domains
+  - resets
+  - ports
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/r8a779g0-sysc.h>
+
+    dsc@feb8d000 {
+        compatible = "renesas,r8a779g0-dsc";
+        reg = <0 0xfeb8d000 0 0x400>;
+        interrupts = <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&cpg CPG_MOD 2819>;
+        power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+        resets = <&cpg 2819>;
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                dsc_in_dsi1: endpoint {
+                    remote-endpoint = <&du_out_dsi1>;
+                };
+            };
+
+            port@1 {
+                reg = <1>;
+                dsc_out_dsi1: endpoint {
+                    remote-endpoint = <&dsi1_in>;
+                };
+            };
+        };
+    };
+...

-- 
2.43.0

[PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Tomi Valkeinen]

From: Marek Vasut <marek.vasut+renesas@mailbox.org>

The Renesas DSC Display Stream Compression is a bridge embedded in the
Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
pass-through bridge and allows DSI1 to be operational on R-Car V4H.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[tomi.valkeinen: use bridge->next_bridge, minor changes]
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
 drivers/gpu/drm/renesas/rcar-du/Kconfig    |  13 +++
 drivers/gpu/drm/renesas/rcar-du/Makefile   |   1 +
 drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c | 163 +++++++++++++++++++++++++++++
 3 files changed, 177 insertions(+)

diff --git a/drivers/gpu/drm/renesas/rcar-du/Kconfig b/drivers/gpu/drm/renesas/rcar-du/Kconfig
index 840305fdeb49..a51f996d3537 100644
--- a/drivers/gpu/drm/renesas/rcar-du/Kconfig
+++ b/drivers/gpu/drm/renesas/rcar-du/Kconfig
@@ -33,6 +33,19 @@ config DRM_RCAR_DW_HDMI
 	help
 	  Enable support for R-Car Gen3 or RZ/G2 internal HDMI encoder.
 
+config DRM_RCAR_USE_DSC
+	bool "R-Car DU DSC Encoder Support"
+	depends on DRM_BRIDGE && OF
+	depends on DRM_RCAR_DU || COMPILE_TEST
+	default DRM_RCAR_DU
+	help
+	  Enable support for the R-Car Display Unit embedded DSC encoder.
+
+config DRM_RCAR_DSC
+	def_tristate DRM_RCAR_DU
+	depends on DRM_RCAR_USE_DSC
+	select RESET_CONTROLLER
+
 config DRM_RCAR_USE_LVDS
 	bool "R-Car DU LVDS Encoder Support"
 	depends on DRM_BRIDGE && OF
diff --git a/drivers/gpu/drm/renesas/rcar-du/Makefile b/drivers/gpu/drm/renesas/rcar-du/Makefile
index 6f132325c8b7..cc27b2265d94 100644
--- a/drivers/gpu/drm/renesas/rcar-du/Makefile
+++ b/drivers/gpu/drm/renesas/rcar-du/Makefile
@@ -12,5 +12,6 @@ rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 obj-$(CONFIG_DRM_RCAR_CMM)		+= rcar_cmm.o
 obj-$(CONFIG_DRM_RCAR_DU)		+= rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI)		+= rcar_dw_hdmi.o
+obj-$(CONFIG_DRM_RCAR_DSC)		+= rcar_dsc.o
 obj-$(CONFIG_DRM_RCAR_LVDS)		+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)		+= rcar_mipi_dsi.o
diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c
new file mode 100644
index 000000000000..2ab5a4bb099c
--- /dev/null
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car DSC Encoder
+ *
+ * Copyright (C) 2025 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_of.h>
+
+struct rcar_dsc {
+	struct drm_bridge bridge;
+
+	struct device *dev;
+	void __iomem *mmio;
+	struct clk *clk;
+	struct reset_control *rst;
+};
+
+static inline struct rcar_dsc *bridge_to_rcar_dsc(struct drm_bridge *bridge)
+{
+	return container_of(bridge, struct rcar_dsc, bridge);
+}
+
+/* -----------------------------------------------------------------------------
+ * Bridge
+ */
+
+static int rcar_dsc_attach(struct drm_bridge *bridge,
+			   struct drm_encoder *encoder,
+			   enum drm_bridge_attach_flags flags)
+{
+	struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
+
+	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
+		return -EINVAL;
+
+	return drm_bridge_attach(encoder, dsc->bridge.next_bridge, bridge,
+				 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
+				   struct drm_atomic_state *state)
+{
+	struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
+
+	WARN_ON(clk_prepare_enable(dsc->clk));
+	WARN_ON(reset_control_deassert(dsc->rst));
+}
+
+static void rcar_dsc_atomic_disable(struct drm_bridge *bridge,
+				    struct drm_atomic_state *state)
+{
+	struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
+
+	reset_control_assert(dsc->rst);
+	clk_disable_unprepare(dsc->clk);
+}
+
+static enum drm_mode_status
+rcar_dsc_bridge_mode_valid(struct drm_bridge *bridge,
+			   const struct drm_display_info *info,
+			   const struct drm_display_mode *mode)
+{
+	if (mode->hdisplay < 320 || mode->hdisplay > 8190)
+		return MODE_BAD_HVALUE;
+
+	if (mode->vdisplay < 160 || mode->vdisplay > 8190)
+		return MODE_BAD_VVALUE;
+
+	if (mode->clock > 400000) /* Really 400 Mpixel/s */
+		return MODE_CLOCK_HIGH;
+
+	return MODE_OK;
+}
+
+static const struct drm_bridge_funcs rcar_dsc_bridge_ops = {
+	.attach = rcar_dsc_attach,
+	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+	.atomic_reset = drm_atomic_helper_bridge_reset,
+	.atomic_enable = rcar_dsc_atomic_enable,
+	.atomic_disable = rcar_dsc_atomic_disable,
+	.mode_valid = rcar_dsc_bridge_mode_valid,
+};
+
+/* -----------------------------------------------------------------------------
+ * Probe & Remove
+ */
+
+static int rcar_dsc_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *remote;
+	struct rcar_dsc *dsc;
+
+	dsc = devm_drm_bridge_alloc(dev, struct rcar_dsc, bridge,
+				    &rcar_dsc_bridge_ops);
+	if (IS_ERR(dsc))
+		return PTR_ERR(dsc);
+
+	platform_set_drvdata(pdev, dsc);
+
+	dsc->dev = &pdev->dev;
+
+	/* Acquire resources. */
+	dsc->mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(dsc->mmio))
+		return PTR_ERR(dsc->mmio);
+
+	dsc->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(dsc->clk))
+		return dev_err_probe(dev, PTR_ERR(dsc->clk),
+				     "Failed to get CPG clock\n");
+
+	dsc->rst = devm_reset_control_get(dev, NULL);
+	if (IS_ERR(dsc->rst))
+		return dev_err_probe(dev, PTR_ERR(dsc->rst),
+				     "Failed to get CPG reset\n");
+
+	remote = of_graph_get_remote_node(dev->of_node, 1, 0);
+	if (!remote)
+		return -EINVAL;
+
+	dsc->bridge.next_bridge = of_drm_find_and_get_bridge(remote);
+	of_node_put(remote);
+	if (!dsc->bridge.next_bridge)
+		return -EPROBE_DEFER;
+
+	dsc->bridge.of_node = dev->of_node;
+
+	return devm_drm_bridge_add(dev, &dsc->bridge);
+}
+
+static const struct of_device_id rcar_dsc_of_table[] = {
+	{ .compatible = "renesas,r8a779g0-dsc" },
+	{}
+};
+
+MODULE_DEVICE_TABLE(of, rcar_dsc_of_table);
+
+static struct platform_driver rcar_dsc_platform_driver = {
+	.probe          = rcar_dsc_probe,
+	.driver         = {
+		.name   = "rcar-dsc",
+		.of_match_table = rcar_dsc_of_table,
+	},
+};
+
+module_platform_driver(rcar_dsc_platform_driver);
+
+MODULE_DESCRIPTION("Renesas R-Car DSC Encoder Driver");
+MODULE_LICENSE("GPL");

-- 
2.43.0

[PATCH 4/5] drm/rcar-du: dsi: Support DSC in the pipeline

[Tomi Valkeinen]

Enabling DSI clocks on rcar-du needs some tricks as the DU dot clock is
provided by the DSI. Thus, we call rcar_mipi_dsi_pclk_enable() from the
crtc, when enabling the crtc.

With DSC (added in upcoming patch) in the pipeline, between the DU and
the DSI, the above call path is broken as the crtc tries to call
rcar_mipi_dsi_pclk_enable() on the DSC.

Adjust the rcar_mipi_dsi_pclk_enable() so that it detects the DSC, and
in that case gets the next bridge from the DSC, which is the DSI.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
 drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c | 36 +++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
index 4ef2e3c129ed..085e229bcb0b 100644
--- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
+++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi.c
@@ -88,6 +88,8 @@ struct dsi_setup_info {
 	const struct dsi_clk_config *clkset;
 };
 
+static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops;
+
 static inline struct rcar_mipi_dsi *
 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
 {
@@ -844,15 +846,39 @@ static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
 	rcar_mipi_dsi_stop_video(dsi);
 }
 
+/*
+ * We need to skip the DSC bridge when we have DSC in between the DU and
+ * the DSI. We detect the DSI bridge via bridge->funcs, and assume the
+ * next_bridge is the DSI bridge. If this is not the case, the DT data
+ * is wrong (so it shouldn't really happen).
+ */
+static struct drm_bridge *
+rcar_mipi_dsi_resolve_bridge(struct drm_bridge *bridge)
+{
+	if (bridge->funcs != &rcar_mipi_dsi_bridge_ops)
+		bridge = bridge->next_bridge;
+
+	if (!bridge || bridge->funcs != &rcar_mipi_dsi_bridge_ops)
+		return NULL;
+
+	return bridge;
+}
+
 void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge,
 			       struct drm_atomic_state *state)
 {
-	struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
 	const struct drm_display_mode *mode;
 	struct drm_connector *connector;
+	struct rcar_mipi_dsi *dsi;
 	struct drm_crtc *crtc;
 	int ret;
 
+	bridge = rcar_mipi_dsi_resolve_bridge(bridge);
+	if (WARN_ON(!bridge))
+		return;
+
+	dsi = bridge_to_rcar_mipi_dsi(bridge);
+
 	connector = drm_atomic_get_new_connector_for_encoder(state,
 							     bridge->encoder);
 	crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
@@ -885,7 +911,13 @@ EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_enable);
 
 void rcar_mipi_dsi_pclk_disable(struct drm_bridge *bridge)
 {
-	struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
+	struct rcar_mipi_dsi *dsi;
+
+	bridge = rcar_mipi_dsi_resolve_bridge(bridge);
+	if (WARN_ON(!bridge))
+		return;
+
+	dsi = bridge_to_rcar_mipi_dsi(bridge);
 
 	rcar_mipi_dsi_shutdown(dsi);
 	rcar_mipi_dsi_clk_disable(dsi);

-- 
2.43.0

[PATCH 5/5] arm64: dts: renesas: Add Renesas R-Car V4H DSC

[Tomi Valkeinen]

From: Marek Vasut <marek.vasut+renesas@mailbox.org>

The Renesas DSC Display Stream Compression is a bridge embedded in the
Renesas R-Car V4H SoC. The bridge is placed between DU and DSI1 units.
Describe the bridge in DT and enable it on Retronix Sparrow Hawk board
to keep DSI1 operational on this board.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a779g0.dtsi          | 31 +++++++++++++++++++++-
 .../boot/dts/renesas/r8a779g3-sparrow-hawk.dts     |  5 ++++
 2 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 82a7278836e5..52a6176f9fd0 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -2298,6 +2298,35 @@ du_out_dsi0: endpoint {
 				port@1 {
 					reg = <1>;
 					du_out_dsi1: endpoint {
+						remote-endpoint = <&dsc_in_dsi1>;
+					};
+				};
+			};
+		};
+
+		dsc: dsc@feb8d000 {
+			compatible = "renesas,r8a779g0-dsc";
+			reg = <0 0xfeb8d000 0 0x400>;
+			interrupts = <GIC_SPI 559 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 2819>;
+			power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+			resets = <&cpg 2819>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					dsc_in_dsi1: endpoint {
+						remote-endpoint = <&du_out_dsi1>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					dsc_out_dsi1: endpoint {
 						remote-endpoint = <&dsi1_in>;
 					};
 				};
@@ -2534,7 +2563,7 @@ ports {
 				port@0 {
 					reg = <0>;
 					dsi1_in: endpoint {
-						remote-endpoint = <&du_out_dsi1>;
+						remote-endpoint = <&dsc_out_dsi1>;
 					};
 				};
 
diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
index 812b133cf29e..f418998c6b05 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts
@@ -288,6 +288,11 @@ channel4 {
 	};
 };
 
+/* Page 27 / DSI to Display */
+&dsc {
+	status = "okay";
+};
+
 /* Page 27 / DSI to Display */
 &dsi1 {
 	status = "okay";

-- 
2.43.0

Re: [PATCH 2/5] dt-bindings: display: bridge: Document Renesas R-Car V4H DSC bindings

[Rob Herring (Arm)]

On Thu, 14 May 2026 15:24:54 +0300, Tomi Valkeinen wrote:
> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
> 
> The Renesas DSC Display Stream Compression is a bridge embedded in the
> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
> 8k or 400 Mpixel/s .
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> [tomi.valkeinen: fix the example]
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> ---
>  .../bindings/display/bridge/renesas,dsc.yaml       | 96 ++++++++++++++++++++++
>  1 file changed, 96 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/bridge/renesas,dsc.example.dtb: dsc@feb8d000 (renesas,r8a779g0-dsc): reg: [[0, 4273524736], [0, 1024]] is too long
	from schema $id: http://devicetree.org/schemas/display/bridge/renesas,dsc.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260514-rcar-du-dsc-v1-2-d65f7a9e9841@ideasonboard.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Geert Uytterhoeven]

Hi Tomi,

On Thu, 14 May 2026 at 14:25, Tomi Valkeinen
<tomi.valkeinen+renesas@ideasonboard.com> wrote:
> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
>
> The Renesas DSC Display Stream Compression is a bridge embedded in the
> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
> pass-through bridge and allows DSI1 to be operational on R-Car V4H.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> [tomi.valkeinen: use bridge->next_bridge, minor changes]
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>

Thanks for your patch!

> --- /dev/null
> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c

> +
> +static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
> +                                  struct drm_atomic_state *state)
> +{
> +       struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
> +
> +       WARN_ON(clk_prepare_enable(dsc->clk));

Who don't you use pm_runtime_resume_and_get() instead, like
rcar_cmm.c? Then you don't need to get the clock at all, and the driver
will keep on working if the DSC ever ends up in a power domain.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Tomi Valkeinen]

Hi Geert,

On 15/05/2026 10:49, Geert Uytterhoeven wrote:
> Hi Tomi,
> 
> On Thu, 14 May 2026 at 14:25, Tomi Valkeinen
> <tomi.valkeinen+renesas@ideasonboard.com> wrote:
>> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
>>
>> The Renesas DSC Display Stream Compression is a bridge embedded in the
>> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
>> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
>> pass-through bridge and allows DSI1 to be operational on R-Car V4H.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
>> [tomi.valkeinen: use bridge->next_bridge, minor changes]
>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> 
> Thanks for your patch!
> 
>> --- /dev/null
>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c
> 
>> +
>> +static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
>> +                                  struct drm_atomic_state *state)
>> +{
>> +       struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
>> +
>> +       WARN_ON(clk_prepare_enable(dsc->clk));

Ah, just missed your comment and sent the v2.

> Who don't you use pm_runtime_resume_and_get() instead, like
> rcar_cmm.c? Then you don't need to get the clock at all, and the driver

Hmm, why wouldn't I need to get the clock? What does the runtime PM do 
on Renesas?

> will keep on working if the DSC ever ends up in a power domain.
I can add runtime PM. I just felt that it was overcomplicating a "dummy" 
driver that just needs to enable the clock when the video pipeline is 
enabled.

  Tomi

Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Geert Uytterhoeven]

Hi Tomi,

On Fri, 15 May 2026 at 10:03, Tomi Valkeinen
<tomi.valkeinen@ideasonboard.com> wrote:
> On 15/05/2026 10:49, Geert Uytterhoeven wrote:
> > On Thu, 14 May 2026 at 14:25, Tomi Valkeinen
> > <tomi.valkeinen+renesas@ideasonboard.com> wrote:
> >> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
> >>
> >> The Renesas DSC Display Stream Compression is a bridge embedded in the
> >> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
> >> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
> >> pass-through bridge and allows DSI1 to be operational on R-Car V4H.
> >>
> >> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> >> [tomi.valkeinen: use bridge->next_bridge, minor changes]
> >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> >
> > Thanks for your patch!
> >
> >> --- /dev/null
> >> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c
> >
> >> +
> >> +static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
> >> +                                  struct drm_atomic_state *state)
> >> +{
> >> +       struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
> >> +
> >> +       WARN_ON(clk_prepare_enable(dsc->clk));
>
> Ah, just missed your comment and sent the v2.
>
> > Who don't you use pm_runtime_resume_and_get() instead, like
> > rcar_cmm.c? Then you don't need to get the clock at all, and the driver
>
> Hmm, why wouldn't I need to get the clock? What does the runtime PM do
> on Renesas?

Runtime PM powers on the power domain (if present), and starts
the device by enabling its module clock.

> > will keep on working if the DSC ever ends up in a power domain.
> I can add runtime PM. I just felt that it was overcomplicating a "dummy"
> driver that just needs to enable the clock when the video pipeline is
> enabled.

Funny, I would say you are overcomplicating a dummy driver by adding
explicit clock control ;-)

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Tomi Valkeinen]

Hi,

On 15/05/2026 11:05, Geert Uytterhoeven wrote:
> Hi Tomi,
> 
> On Fri, 15 May 2026 at 10:03, Tomi Valkeinen
> <tomi.valkeinen@ideasonboard.com> wrote:
>> On 15/05/2026 10:49, Geert Uytterhoeven wrote:
>>> On Thu, 14 May 2026 at 14:25, Tomi Valkeinen
>>> <tomi.valkeinen+renesas@ideasonboard.com> wrote:
>>>> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
>>>>
>>>> The Renesas DSC Display Stream Compression is a bridge embedded in the
>>>> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
>>>> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
>>>> pass-through bridge and allows DSI1 to be operational on R-Car V4H.
>>>>
>>>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
>>>> [tomi.valkeinen: use bridge->next_bridge, minor changes]
>>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
>>>
>>> Thanks for your patch!
>>>
>>>> --- /dev/null
>>>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c
>>>
>>>> +
>>>> +static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
>>>> +                                  struct drm_atomic_state *state)
>>>> +{
>>>> +       struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
>>>> +
>>>> +       WARN_ON(clk_prepare_enable(dsc->clk));
>>
>> Ah, just missed your comment and sent the v2.
>>
>>> Who don't you use pm_runtime_resume_and_get() instead, like
>>> rcar_cmm.c? Then you don't need to get the clock at all, and the driver
>>
>> Hmm, why wouldn't I need to get the clock? What does the runtime PM do
>> on Renesas?
> 
> Runtime PM powers on the power domain (if present), and starts
> the device by enabling its module clock.
> 
>>> will keep on working if the DSC ever ends up in a power domain.
>> I can add runtime PM. I just felt that it was overcomplicating a "dummy"
>> driver that just needs to enable the clock when the video pipeline is
>> enabled.
> 
> Funny, I would say you are overcomplicating a dummy driver by adding
> explicit clock control ;-)
Well, now that I know the runtime PM does magics behind the scenes, you 
are right =).

How's "module clock" defined? Is it the first clock in the clocks DT 
property?

I'll have a look at whitehawk too. The funny thing is, I had a 
recollection that dsc was somehow used on whitehawk too. I looked at the 
board, and saw only the single mini DP connector on the CPU board, which 
already works, so I then concluded that the other DSI path is for the 
GMSL... I think I need new eyeglasses.

  Tomi

Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Geert Uytterhoeven]

Hi Tomi,

On Fri, 15 May 2026 at 10:17, Tomi Valkeinen
<tomi.valkeinen@ideasonboard.com> wrote:
> On 15/05/2026 11:05, Geert Uytterhoeven wrote:
> > On Fri, 15 May 2026 at 10:03, Tomi Valkeinen
> > <tomi.valkeinen@ideasonboard.com> wrote:
> >> On 15/05/2026 10:49, Geert Uytterhoeven wrote:
> >>> On Thu, 14 May 2026 at 14:25, Tomi Valkeinen
> >>> <tomi.valkeinen+renesas@ideasonboard.com> wrote:
> >>>> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
> >>>>
> >>>> The Renesas DSC Display Stream Compression is a bridge embedded in the
> >>>> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
> >>>> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
> >>>> pass-through bridge and allows DSI1 to be operational on R-Car V4H.
> >>>>
> >>>> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> >>>> [tomi.valkeinen: use bridge->next_bridge, minor changes]
> >>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> >>>
> >>> Thanks for your patch!
> >>>
> >>>> --- /dev/null
> >>>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c
> >>>
> >>>> +
> >>>> +static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
> >>>> +                                  struct drm_atomic_state *state)
> >>>> +{
> >>>> +       struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
> >>>> +
> >>>> +       WARN_ON(clk_prepare_enable(dsc->clk));
> >>
> >> Ah, just missed your comment and sent the v2.
> >>
> >>> Who don't you use pm_runtime_resume_and_get() instead, like
> >>> rcar_cmm.c? Then you don't need to get the clock at all, and the driver
> >>
> >> Hmm, why wouldn't I need to get the clock? What does the runtime PM do
> >> on Renesas?
> >
> > Runtime PM powers on the power domain (if present), and starts
> > the device by enabling its module clock.
> >
> >>> will keep on working if the DSC ever ends up in a power domain.
> >> I can add runtime PM. I just felt that it was overcomplicating a "dummy"
> >> driver that just needs to enable the clock when the video pipeline is
> >> enabled.
> >
> > Funny, I would say you are overcomplicating a dummy driver by adding
> > explicit clock control ;-)
> Well, now that I know the runtime PM does magics behind the scenes, you
> are right =).
>
> How's "module clock" defined? Is it the first clock in the clocks DT
> property?

It's the clock pointing to the cpg device node, and having "CPG_MOD"
as its first cell.  Usually it's the first clock.  Note that e.g. the
DU is special, as it' is represented by a single device node with
multiple module clocks (and multiple (but less) resets), due to the
tight integration between the individual channels.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/5] drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Philipp Zabel]

On Do, 2026-05-14 at 15:24 +0300, Tomi Valkeinen wrote:
> From: Marek Vasut <marek.vasut+renesas@mailbox.org>
> 
> The Renesas DSC Display Stream Compression is a bridge embedded in the
> Renesas R-Car V4H SoC. The bridge performs VESA DSC encoding of up to
> 8k or 400 Mpixel/s . Add rudimentary driver, which currently acts as a
> pass-through bridge and allows DSI1 to be operational on R-Car V4H.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
> [tomi.valkeinen: use bridge->next_bridge, minor changes]
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
> ---
>  drivers/gpu/drm/renesas/rcar-du/Kconfig    |  13 +++
>  drivers/gpu/drm/renesas/rcar-du/Makefile   |   1 +
>  drivers/gpu/drm/renesas/rcar-du/rcar_dsc.c | 163 +++++++++++++++++++++++++++++
>  3 files changed, 177 insertions(+)
> 
> diff --git a/drivers/gpu/drm/renesas/rcar-du/Kconfig b/drivers/gpu/drm/renesas/rcar-du/Kconfig
> index 840305fdeb49..a51f996d3537 100644
> --- a/drivers/gpu/drm/renesas/rcar-du/Kconfig
> +++ b/drivers/gpu/drm/renesas/rcar-du/Kconfig
> @@ -33,6 +33,19 @@ config DRM_RCAR_DW_HDMI
>  	help
>  	  Enable support for R-Car Gen3 or RZ/G2 internal HDMI encoder.
>  
> +config DRM_RCAR_USE_DSC
> +	bool "R-Car DU DSC Encoder Support"
> +	depends on DRM_BRIDGE && OF
> +	depends on DRM_RCAR_DU || COMPILE_TEST
> +	default DRM_RCAR_DU
> +	help
> +	  Enable support for the R-Car Display Unit embedded DSC encoder.
> +
> +config DRM_RCAR_DSC
> +	def_tristate DRM_RCAR_DU
> +	depends on DRM_RCAR_USE_DSC
> +	select RESET_CONTROLLER

No need to select RESET_CONTROLLER, the API is stubbed out if not
enabled.

regards
Philipp

Claude review: drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Claude Code Review Bot]

Patch Review

This is the core driver and has several items worth addressing:

**Bridge reference leak**: `of_drm_find_and_get_bridge()` increments the bridge refcount (as documented: "The refcount of the returned bridge is incremented. Use drm_bridge_put() when done with it."). The driver never calls `drm_bridge_put()` on `dsc->bridge.next_bridge`, leaking the reference. Compare with `rcar_lvds.c` which properly calls `drm_bridge_put(lvds->companion)` in its destroy callback for bridges obtained via `of_drm_find_and_get_bridge()`. This should be fixed.

```c
+	dsc->bridge.next_bridge = of_drm_find_and_get_bridge(remote);
+	of_node_put(remote);
+	if (!dsc->bridge.next_bridge)
+		return -EPROBE_DEFER;
```

**Use `devm_pm_runtime_enable`**: The probe/remove pair of `pm_runtime_enable` / `pm_runtime_disable` can be replaced with `devm_pm_runtime_enable(&pdev->dev)` in probe, eliminating the need for `rcar_dsc_remove()` entirely. This is the modern pattern and avoids ordering bugs.

```c
+static void rcar_dsc_remove(struct platform_device *pdev)
+{
+	pm_runtime_disable(&pdev->dev);
+}
```

**`-EPROBE_DEFER` without `dev_err_probe`**: When `of_drm_find_and_get_bridge()` returns NULL, the driver returns `-EPROBE_DEFER` silently. Using `return dev_err_probe(dev, -EPROBE_DEFER, "failed to find next bridge\n")` would suppress the message during deferred probing but log it if probe ultimately fails, which aids debugging.

**Unused MMIO mapping**: `dsc->mmio` is mapped but never accessed since this is bypass-mode only. This is fine for a rudimentary/initial driver, but it would be helpful to add a brief note in the commit message that the MMIO is mapped for future DSC encoding support. (No code change needed, just a documentation note.)

**`mode_valid` clock check**: The comment says "Really 400 Mpixel/s" but `mode->clock` is in kHz, and the check `mode->clock > 400000` limits to 400 MHz pixel clock. Whether 400 MHz clock equals 400 Mpixel/s depends on the pixel format — they're the same only for single-pixel-per-clock. If the hardware limit is truly 400 Mpixel/s and the DSC block always processes one pixel per clock, the check is correct. Worth confirming this assumption.

```c
+	if (mode->clock > 400000) /* Really 400 Mpixel/s */
+		return MODE_CLOCK_HIGH;
```

---
Generated by Claude Code Patch Reviewer

Claude review: drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Claude Code Review Bot]

Patch Review

**Status: Needs minor fixes**

**Error handling in atomic_enable:**

```c
+static void rcar_dsc_atomic_enable(struct drm_bridge *bridge,
+				   struct drm_atomic_state *state)
+{
+	struct rcar_dsc *dsc = bridge_to_rcar_dsc(bridge);
+
+	WARN_ON(clk_prepare_enable(dsc->clk));
+	WARN_ON(reset_control_deassert(dsc->rst));
+}
```

If `clk_prepare_enable()` fails, the code still proceeds to deassert the reset. The reset deassert will also likely fail or leave things in an inconsistent state. Consider returning early on clock failure:

```c
if (WARN_ON(clk_prepare_enable(dsc->clk)))
    return;
WARN_ON(reset_control_deassert(dsc->rst));
```

**Bridge reference for next_bridge:**

```c
+	dsc->bridge.next_bridge = of_drm_find_and_get_bridge(remote);
+	of_node_put(remote);
+	if (!dsc->bridge.next_bridge)
+		return -EPROBE_DEFER;
```

The use of `of_drm_find_and_get_bridge()` with direct assignment to `bridge.next_bridge` is correct — the bridge core will put the reference on bridge destruction. Using `devm_drm_of_get_bridge()` here would cause a double-put. Good.

However, returning `-EPROBE_DEFER` unconditionally for NULL means a DT misconfiguration (e.g. output port pointing to a non-bridge node) would cause infinite probe deferral. This is a common pattern in DRM drivers though, so it's acceptable, just worth being aware of.

**Unused mmio mapping:**

```c
+	dsc->mmio = devm_platform_ioremap_resource(pdev, 0);
```

The `mmio` is mapped but never read or written since the driver only operates in bypass mode. This is fine for correctness (it validates the resource exists), but could also be deferred to when DSC encoding support is added. Not a blocking issue.

**Kconfig structure:**

The two-config pattern (`DRM_RCAR_USE_DSC` bool + `DRM_RCAR_DSC` def_tristate) matches the existing pattern used by LVDS and MIPI DSI in this directory. The `select RESET_CONTROLLER` is appropriate.

---

---
Generated by Claude Code Patch Reviewer

Claude review: drm/rcar-du: Add support for DSI pipelines with DSC

[Claude Code Review Bot]

Overall Series Review

Subject: drm/rcar-du: Add support for DSI pipelines with DSC
Author: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Patches: 13
Reviewed: 2026-05-16T10:53:54.718447

---

This is a 5-patch series adding basic DSC (Display Stream Compression) bypass support for the R-Car V4H (R8A779G0) SoC. The DSC IP block sits between the DU and DSI1, and even when DSC encoding isn't needed, the block must be enabled for DSI1 output to work. The series adds a clock, DT bindings, a passthrough bridge driver, wiring in the DSI driver to handle the new bridge in the chain, and DTS entries.

Overall the series is sensible and well-structured. The approach of implementing a minimal pass-through bridge is appropriate for an initial enablement. There is one notable bug (bridge reference leak in the DSC driver) and a few minor items worth addressing.

**Verdict: Needs minor fixes before merge.**

---

---
Generated by Claude Code Patch Reviewer

Claude review: clk: renesas: r8a779g0: Add DSC clock

[Claude Code Review Bot]

Patch Review

**Status: Looks good.**

Straightforward one-liner adding the DSC module clock:

```c
DEF_MOD("dsc",		2819,	R8A779G0_CLK_VIOBUSD2),
```

The module ID 2819 and parent clock `R8A779G0_CLK_VIOBUSD2` are consistent with the DSC being in the video I/O domain. Insertion point maintains alphabetical/numerical ordering with surrounding entries (2723 tsn, 2926 ssiu). No issues.

---

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: bridge: Document Renesas R-Car V4H DSC bindings

[Claude Code Review Bot]

Patch Review

**Status: Minor comments.**

The binding is well-structured. A few observations:

1. The binding lists `interrupts` as required, but the DSC driver (patch 3) never registers an interrupt handler. If the driver doesn't use interrupts today and this is just for completeness/future use, that's fine, but it's worth noting. Conversely, if the interrupt line is genuinely required for the hardware to function, the driver should at least request it to ensure the interrupt controller configures it properly.

2. The `ports` schema correctly uses `$ref: /schemas/graph.yaml#/properties/ports` and requires both ports. The top-level `unevaluatedProperties: false` is correct here.

3. The example is well-formed and consistent with the SoC DTS added in patch 5.

---

---
Generated by Claude Code Patch Reviewer

Claude review: drm/rcar-du: dsc: Add rudimentary Renesas R-Car V4H DSC driver

[Claude Code Review Bot]

Patch Review

**Status: Has a bug and minor issues.**

**Bug - Bridge reference leak:**

```c
dsc->bridge.next_bridge = of_drm_find_and_get_bridge(remote);
of_node_put(remote);
if (!dsc->bridge.next_bridge)
    return -EPROBE_DEFER;
```

`of_drm_find_and_get_bridge()` takes a reference on the returned bridge (via `drm_bridge_get()`), but there is no corresponding `drm_bridge_put()` anywhere in the driver. There is no `.remove` callback and no devm cleanup for this reference. Compare with `rcar_du_encoder.c` which properly calls `drm_bridge_put()` on its stored bridge references during cleanup.

The existing `rcar_mipi_dsi.c` uses `devm_drm_of_get_bridge()` for its `next_bridge`, which handles cleanup automatically. This driver should do the same:

```c
dsc->bridge.next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
if (IS_ERR(dsc->bridge.next_bridge))
    return dev_err_probe(dev, PTR_ERR(dsc->bridge.next_bridge),
                         "Failed to get next bridge\n");
```

Note: `devm_drm_of_get_bridge()` returns `ERR_PTR` (not NULL), so the error check would need to change accordingly.

**Minor - Error swallowing in atomic_enable:**

```c
WARN_ON(clk_prepare_enable(dsc->clk));
WARN_ON(reset_control_deassert(dsc->rst));
```

If `clk_prepare_enable()` fails, `reset_control_deassert()` still runs on a potentially non-clocked block. These should be sequenced with early return on failure. Though this pattern is common in bridge `atomic_enable` (where you can't return errors), at minimum the reset deassert should be conditional on clock enable succeeding.

**Minor - mode_valid comment:**

```c
if (mode->clock > 400000) /* Really 400 Mpixel/s */
    return MODE_CLOCK_HIGH;
```

The comment "Really 400 Mpixel/s" is slightly confusing. `mode->clock` is in kHz, so 400000 kHz = 400 MHz. For 1 pixel/clock this is indeed 400 Mpixel/s. The comment could be clearer: perhaps "400 MHz pixel clock = 400 Mpixel/s".

**Minor - mmio mapped but unused:**

```c
dsc->mmio = devm_platform_ioremap_resource(pdev, 0);
```

The `mmio` field is mapped but never read from or written to in this driver (bypass mode doesn't touch any registers). This is fine as scaffolding for future DSC encoding support, but worth noting.

---

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Generated by Claude Code Patch Reviewer

Claude review: drm/rcar-du: dsi: Support DSC in the pipeline

[Claude Code Review Bot]

Patch Review

**Status: Design concern, otherwise fine.**

The core approach is pragmatic: when the CRTC calls `rcar_mipi_dsi_pclk_enable()` with a bridge that might be the DSC (not DSI), resolve through to the actual DSI bridge by checking `bridge->funcs`:

```c
static struct drm_bridge *
rcar_mipi_dsi_resolve_bridge(struct drm_bridge *bridge)
{
    if (bridge->funcs != &rcar_mipi_dsi_bridge_ops)
        bridge = bridge->next_bridge;

    if (!bridge || bridge->funcs != &rcar_mipi_dsi_bridge_ops)
        return NULL;

    return bridge;
}
```

**Design concern - function pointer comparison for bridge identification:**

Comparing `bridge->funcs` against `&rcar_mipi_dsi_bridge_ops` works but creates a tight coupling between the DSI driver and whatever bridges might appear in the chain. If another bridge type were ever inserted, this would break silently. The comment correctly acknowledges this:

```c
/* We detect the DSI bridge via bridge->funcs, and assume the
 * next_bridge is the DSI bridge. */
```

An alternative would be to walk the bridge chain until a DSI bridge is found (checking all bridges, not just the first two). However, for this specific hardware topology where there's at most one intermediate bridge, the current approach is acceptable. Just be aware this won't generalize.

**Minor:** The forward declaration of `rcar_mipi_dsi_bridge_ops` is necessary and correct:

```c
static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops;
```

The function is used before its definition, so this is fine.

---

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Generated by Claude Code Patch Reviewer

Claude review: arm64: dts: renesas: Add Renesas R-Car V4H DSC

[Claude Code Review Bot]

Patch Review

**Status: Looks good.**

The DTS changes correctly wire the DSC into the pipeline between DU and DSI1:

- `du_out_dsi1` now points to `dsc_in_dsi1` (was `dsi1_in`)
- DSC port@0 input connects to DU, port@1 output connects to DSI1
- `dsi1_in` now points to `dsc_out_dsi1` (was `du_out_dsi1`)

The DSC node is `status = "disabled"` by default in the SoC dtsi, and the Sparrow Hawk board dts enables it:

```dts
&dsc {
    status = "okay";
};
```

One observation: this inserts the DSC unconditionally into the DSI1 pipeline at the SoC level. This means every board using DSI1 on this SoC must now also enable the DSC node. The cover letter confirms this matches the hardware topology (DSC is always between DU and DSI1 on V4H). The `status = "disabled"` default handles boards that don't use DSI1 at all.

The node placement and properties (clocks, power-domains, resets matching module ID 2819 from patch 1) are consistent with the binding from patch 2.

---

**Summary of required changes:**
1. **Patch 3:** Fix the bridge reference leak - use `devm_drm_of_get_bridge()` instead of `of_drm_find_and_get_bridge()`, or add explicit cleanup via `drm_bridge_put()`.

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Generated by Claude Code Patch Reviewer