Claude review: arm64: dts: qcom: Add GPU support for Glymur

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Summary:** Adds the GPU and GMU DT nodes with OPP tables, interconnects, and IOMMU references.

The GPU node at `0x3d00000` (size `0x6c000`) and GMU at `0x3d6c000` (size `0x32000`) are contiguous and non-overlapping:
- GPU: `0x3d00000` – `0x3d6bfff`
- GMU: `0x3d6c000` – `0x3d9dfff`
- cx_mem: `0x3d9e000` – `0x3d9ffff`

The RSCC at `gpu_base + 0x50000 = 0x3d50000` falls within the GPU kgsl_3d0_reg_memory range, consistent with patch 1.

The GPU OPP table has 12 entries ranging from 310 MHz to 1850 MHz (the cover letter's claimed max Fmax). The higher OPPs (1550+ MHz) use `opp-supported-hw = <0x7>` and `<0x3>` to restrict to specific speedbins — this is standard practice.

The GMU OPP table has 4 entries (575–750 MHz), which is reasonable.

**Observation:** The GMU register range (`0x3d6c000`, size `0x32000`, ending at `0x3d9dfff`) overlaps with `gpucc` at `0x3d90000` (size `0x9800`). This is likely intentional — the GMU driver only accesses its own registers within this range, and the clock controller has a separate ioremap. This pattern appears in other Qualcomm SoCs. Mentioned for completeness only.

Already has Reviewed-by from Konrad Dybcio.

No blocking issues.

---
Generated by Claude Code Patch Reviewer