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* [PATCH] accel/ivpu: Remove disable_d0i3_msg workaround
@ 2026-05-26 12:55 Andrzej Kacprowski
  2026-05-26 13:03 ` Wachowski, Karol
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Andrzej Kacprowski @ 2026-05-26 12:55 UTC (permalink / raw)
  To: dri-devel
  Cc: oded.gabbay, jeff.hugo, karol.wachowski, lizhi.hou,
	andrzej.kacprowski

All published NPU firmware versions support D0i3 delayed entry
flow, making this workaround obsolete. It was originally added as
a safety measure for potential firmware bugs.

Recent firmware dropped legacy D0i3 entry support, so the workaround
can't be used anyway. Hardcode d0i3_delayed_entry boot param to 1 to
ensure older firmware works in the correct mode.

No functional changes, just dead code cleanup.

Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_drv.h     |  3 ---
 drivers/accel/ivpu/ivpu_fw.c      | 23 ++---------------------
 drivers/accel/ivpu/ivpu_jsm_msg.c |  3 ---
 drivers/accel/ivpu/vpu_boot_api.h |  6 ++++--
 4 files changed, 6 insertions(+), 29 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_drv.h b/drivers/accel/ivpu/ivpu_drv.h
index c77dde310e81..9eefbbb7ba11 100644
--- a/drivers/accel/ivpu/ivpu_drv.h
+++ b/drivers/accel/ivpu/ivpu_drv.h
@@ -111,7 +111,6 @@ struct ivpu_wa_table {
 	bool clear_runtime_mem;
 	bool interrupt_clear_with_0;
 	bool disable_clock_relinquish;
-	bool disable_d0i3_msg;
 	bool wp0_during_power_up;
 	bool disable_d0i2;
 };
@@ -220,8 +219,6 @@ extern bool ivpu_force_snoop;
 #define IVPU_TEST_MODE_FW_TEST            BIT(0)
 #define IVPU_TEST_MODE_NULL_HW            BIT(1)
 #define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
-#define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
-#define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
 #define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
 #define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
 #define IVPU_TEST_MODE_TURBO_ENABLE       BIT(9)
diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c
index 107f8ad31050..7db199e04f7c 100644
--- a/drivers/accel/ivpu/ivpu_fw.c
+++ b/drivers/accel/ivpu/ivpu_fw.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (C) 2020-2025 Intel Corporation
+ * Copyright (C) 2020-2026 Intel Corporation
  */
 
 #include <linux/firmware.h>
@@ -347,22 +347,6 @@ static void ivpu_fw_release(struct ivpu_device *vdev)
 	release_firmware(vdev->fw->file);
 }
 
-/* Initialize workarounds that depend on FW version */
-static void
-ivpu_fw_init_wa(struct ivpu_device *vdev)
-{
-	const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
-
-	if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
-	    (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
-		vdev->wa.disable_d0i3_msg = true;
-
-	/* Force enable the feature for testing purposes */
-	if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
-		vdev->wa.disable_d0i3_msg = false;
-
-	IVPU_PRINT_WA(disable_d0i3_msg);
-}
 
 static int ivpu_fw_mem_init(struct ivpu_device *vdev)
 {
@@ -480,8 +464,6 @@ int ivpu_fw_init(struct ivpu_device *vdev)
 	if (ret)
 		goto err_fw_release;
 
-	ivpu_fw_init_wa(vdev);
-
 	ret = ivpu_fw_mem_init(vdev);
 	if (ret)
 		goto err_fw_release;
@@ -711,8 +693,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
 	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
 		boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
 	boot_params->dvfs_mode = vdev->fw->dvfs_mode;
-	if (!IVPU_WA(disable_d0i3_msg))
-		boot_params->d0i3_delayed_entry = 1;
+	boot_params->d0i3_delayed_entry = 1;
 	boot_params->d0i3_residency_time_us = 0;
 	boot_params->d0i3_entry_vpu_ts = 0;
 	if (IVPU_WA(disable_d0i2))
diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.c b/drivers/accel/ivpu/ivpu_jsm_msg.c
index 17b42a76aef9..6361fe50596e 100644
--- a/drivers/accel/ivpu/ivpu_jsm_msg.c
+++ b/drivers/accel/ivpu/ivpu_jsm_msg.c
@@ -275,9 +275,6 @@ int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev)
 	struct vpu_jsm_msg resp;
 	int ret;
 
-	if (IVPU_WA(disable_d0i3_msg))
-		return 0;
-
 	req.payload.pwr_d0i3_enter.send_response = 1;
 
 	ret = ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_PWR_D0I3_ENTER_DONE, &resp,
diff --git a/drivers/accel/ivpu/vpu_boot_api.h b/drivers/accel/ivpu/vpu_boot_api.h
index a41170bbc6b7..06c092d5e675 100644
--- a/drivers/accel/ivpu/vpu_boot_api.h
+++ b/drivers/accel/ivpu/vpu_boot_api.h
@@ -41,7 +41,7 @@
 /**
  * API header changed (field names, documentation, formatting) but API itself has not been changed
  */
-#define VPU_BOOT_API_VER_PATCH 4
+#define VPU_BOOT_API_VER_PATCH 5
 
 /**
  * Index in the API version table
@@ -320,9 +320,11 @@ struct vpu_boot_params {
 	u64 dvfs_param;
 	/**
 	 * D0i3 delayed entry
-	 * Bit0: Disable CPU state save on D0i2 entry flow.
+	 * Bit 0: Disable CPU state save on D0i2 entry flow.
 	 *       0: Every D0i2 entry saves state. Save state IPC message ignored.
 	 *       1: IPC message required to save state on D0i3 entry flow.
+	 * NOTE: This parameter is deprecated starting NPU50xx+. Bit 0 is now hardcoded to 1,
+	 * meaning CPU state save always requires IPC message on D0i3 entry flow.
 	 */
 	u32 d0i3_delayed_entry;
 	/** Time spent by VPU in D0i3 state */
-- 
2.43.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] accel/ivpu: Remove disable_d0i3_msg workaround
  2026-05-26 12:55 [PATCH] accel/ivpu: Remove disable_d0i3_msg workaround Andrzej Kacprowski
@ 2026-05-26 13:03 ` Wachowski, Karol
  2026-05-27  4:51 ` Claude review: " Claude Code Review Bot
  2026-05-27  4:51 ` Claude Code Review Bot
  2 siblings, 0 replies; 4+ messages in thread
From: Wachowski, Karol @ 2026-05-26 13:03 UTC (permalink / raw)
  To: Andrzej Kacprowski, dri-devel; +Cc: oded.gabbay, jeff.hugo, lizhi.hou

On 26-May-26 14:55, Andrzej Kacprowski wrote:
> All published NPU firmware versions support D0i3 delayed entry
> flow, making this workaround obsolete. It was originally added as
> a safety measure for potential firmware bugs.
> 
> Recent firmware dropped legacy D0i3 entry support, so the workaround
> can't be used anyway. Hardcode d0i3_delayed_entry boot param to 1 to
> ensure older firmware works in the correct mode.
> 
> No functional changes, just dead code cleanup.
> 
> Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
> ---

Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com>

>   drivers/accel/ivpu/ivpu_drv.h     |  3 ---
>   drivers/accel/ivpu/ivpu_fw.c      | 23 ++---------------------
>   drivers/accel/ivpu/ivpu_jsm_msg.c |  3 ---
>   drivers/accel/ivpu/vpu_boot_api.h |  6 ++++--
>   4 files changed, 6 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/accel/ivpu/ivpu_drv.h b/drivers/accel/ivpu/ivpu_drv.h
> index c77dde310e81..9eefbbb7ba11 100644
> --- a/drivers/accel/ivpu/ivpu_drv.h
> +++ b/drivers/accel/ivpu/ivpu_drv.h
> @@ -111,7 +111,6 @@ struct ivpu_wa_table {
>   	bool clear_runtime_mem;
>   	bool interrupt_clear_with_0;
>   	bool disable_clock_relinquish;
> -	bool disable_d0i3_msg;
>   	bool wp0_during_power_up;
>   	bool disable_d0i2;
>   };
> @@ -220,8 +219,6 @@ extern bool ivpu_force_snoop;
>   #define IVPU_TEST_MODE_FW_TEST            BIT(0)
>   #define IVPU_TEST_MODE_NULL_HW            BIT(1)
>   #define IVPU_TEST_MODE_NULL_SUBMISSION    BIT(2)
> -#define IVPU_TEST_MODE_D0I3_MSG_DISABLE   BIT(4)
> -#define IVPU_TEST_MODE_D0I3_MSG_ENABLE    BIT(5)
>   #define IVPU_TEST_MODE_MIP_DISABLE        BIT(6)
>   #define IVPU_TEST_MODE_DISABLE_TIMEOUTS   BIT(8)
>   #define IVPU_TEST_MODE_TURBO_ENABLE       BIT(9)
> diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c
> index 107f8ad31050..7db199e04f7c 100644
> --- a/drivers/accel/ivpu/ivpu_fw.c
> +++ b/drivers/accel/ivpu/ivpu_fw.c
> @@ -1,6 +1,6 @@
>   // SPDX-License-Identifier: GPL-2.0-only
>   /*
> - * Copyright (C) 2020-2025 Intel Corporation
> + * Copyright (C) 2020-2026 Intel Corporation
>    */
>   
>   #include <linux/firmware.h>
> @@ -347,22 +347,6 @@ static void ivpu_fw_release(struct ivpu_device *vdev)
>   	release_firmware(vdev->fw->file);
>   }
>   
> -/* Initialize workarounds that depend on FW version */
> -static void
> -ivpu_fw_init_wa(struct ivpu_device *vdev)
> -{
> -	const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data;
> -
> -	if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) ||
> -	    (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE))
> -		vdev->wa.disable_d0i3_msg = true;
> -
> -	/* Force enable the feature for testing purposes */
> -	if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE)
> -		vdev->wa.disable_d0i3_msg = false;
> -
> -	IVPU_PRINT_WA(disable_d0i3_msg);
> -}
>   
>   static int ivpu_fw_mem_init(struct ivpu_device *vdev)
>   {
> @@ -480,8 +464,6 @@ int ivpu_fw_init(struct ivpu_device *vdev)
>   	if (ret)
>   		goto err_fw_release;
>   
> -	ivpu_fw_init_wa(vdev);
> -
>   	ret = ivpu_fw_mem_init(vdev);
>   	if (ret)
>   		goto err_fw_release;
> @@ -711,8 +693,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params
>   	if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW)
>   		boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS;
>   	boot_params->dvfs_mode = vdev->fw->dvfs_mode;
> -	if (!IVPU_WA(disable_d0i3_msg))
> -		boot_params->d0i3_delayed_entry = 1;
> +	boot_params->d0i3_delayed_entry = 1;
>   	boot_params->d0i3_residency_time_us = 0;
>   	boot_params->d0i3_entry_vpu_ts = 0;
>   	if (IVPU_WA(disable_d0i2))
> diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.c b/drivers/accel/ivpu/ivpu_jsm_msg.c
> index 17b42a76aef9..6361fe50596e 100644
> --- a/drivers/accel/ivpu/ivpu_jsm_msg.c
> +++ b/drivers/accel/ivpu/ivpu_jsm_msg.c
> @@ -275,9 +275,6 @@ int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev)
>   	struct vpu_jsm_msg resp;
>   	int ret;
>   
> -	if (IVPU_WA(disable_d0i3_msg))
> -		return 0;
> -
>   	req.payload.pwr_d0i3_enter.send_response = 1;
>   
>   	ret = ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_PWR_D0I3_ENTER_DONE, &resp,
> diff --git a/drivers/accel/ivpu/vpu_boot_api.h b/drivers/accel/ivpu/vpu_boot_api.h
> index a41170bbc6b7..06c092d5e675 100644
> --- a/drivers/accel/ivpu/vpu_boot_api.h
> +++ b/drivers/accel/ivpu/vpu_boot_api.h
> @@ -41,7 +41,7 @@
>   /**
>    * API header changed (field names, documentation, formatting) but API itself has not been changed
>    */
> -#define VPU_BOOT_API_VER_PATCH 4
> +#define VPU_BOOT_API_VER_PATCH 5
>   
>   /**
>    * Index in the API version table
> @@ -320,9 +320,11 @@ struct vpu_boot_params {
>   	u64 dvfs_param;
>   	/**
>   	 * D0i3 delayed entry
> -	 * Bit0: Disable CPU state save on D0i2 entry flow.
> +	 * Bit 0: Disable CPU state save on D0i2 entry flow.
>   	 *       0: Every D0i2 entry saves state. Save state IPC message ignored.
>   	 *       1: IPC message required to save state on D0i3 entry flow.
> +	 * NOTE: This parameter is deprecated starting NPU50xx+. Bit 0 is now hardcoded to 1,
> +	 * meaning CPU state save always requires IPC message on D0i3 entry flow.
>   	 */
>   	u32 d0i3_delayed_entry;
>   	/** Time spent by VPU in D0i3 state */


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Claude review: accel/ivpu: Remove disable_d0i3_msg workaround
  2026-05-26 12:55 [PATCH] accel/ivpu: Remove disable_d0i3_msg workaround Andrzej Kacprowski
  2026-05-26 13:03 ` Wachowski, Karol
@ 2026-05-27  4:51 ` Claude Code Review Bot
  2026-05-27  4:51 ` Claude Code Review Bot
  2 siblings, 0 replies; 4+ messages in thread
From: Claude Code Review Bot @ 2026-05-27  4:51 UTC (permalink / raw)
  To: dri-devel-reviews

Overall Series Review

Subject: accel/ivpu: Remove disable_d0i3_msg workaround
Author: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com>
Patches: 2
Reviewed: 2026-05-27T14:51:17.107370

---

This is a single, well-scoped cleanup patch that removes the `disable_d0i3_msg` workaround from the Intel VPU (NPU) accelerator driver. The rationale is clear: all published firmware versions support D0i3 delayed entry, and newer firmware has dropped the legacy path entirely, making the workaround dead code.

The patch is **straightforward and correct**. All references to the workaround are consistently removed across all four files — the workaround flag in the WA table, the test mode bits, the initialization function, the conditional in boot params setup, and the early-return guard in the JSM D0i3 entry path. The `d0i3_delayed_entry` boot param is now unconditionally set to 1, which is the safe/correct value for all supported firmware.

The patch also bumps the boot API patch version (4 → 5) and updates the documentation comment for the `d0i3_delayed_entry` field to note deprecation on NPU50xx+, which is a good practice.

**No bugs or issues found.** This is a clean removal of dead code with no functional concerns.

---
Generated by Claude Code Patch Reviewer

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Claude review: accel/ivpu: Remove disable_d0i3_msg workaround
  2026-05-26 12:55 [PATCH] accel/ivpu: Remove disable_d0i3_msg workaround Andrzej Kacprowski
  2026-05-26 13:03 ` Wachowski, Karol
  2026-05-27  4:51 ` Claude review: " Claude Code Review Bot
@ 2026-05-27  4:51 ` Claude Code Review Bot
  2 siblings, 0 replies; 4+ messages in thread
From: Claude Code Review Bot @ 2026-05-27  4:51 UTC (permalink / raw)
  To: dri-devel-reviews

Patch Review

**Verdict: Looks good.**

**ivpu_drv.h changes:**
- Removes `bool disable_d0i3_msg;` from `struct ivpu_wa_table` — correct, the field is no longer referenced anywhere.
- Removes `IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4)` and `IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5)` — correct. Note that BIT(4) and BIT(5) are now unused in the test_mode space, which is fine since these are bitmask values and the remaining bits (0-2, 6, 8, 9) keep their positions.

**ivpu_fw.c changes:**
- The entire `ivpu_fw_init_wa()` function is removed. I confirmed via grep that `disable_d0i3_msg` was the **only** workaround handled in this function, so removing the whole function is correct. If this function had handled other workarounds, removing it would have been a bug.
- The call `ivpu_fw_init_wa(vdev)` in `ivpu_fw_init()` is removed — matches the function removal.
- The conditional:
  ```c
  if (!IVPU_WA(disable_d0i3_msg))
      boot_params->d0i3_delayed_entry = 1;
  ```
  is simplified to:
  ```c
  boot_params->d0i3_delayed_entry = 1;
  ```
  This unconditionally enables delayed entry, which the commit message explains is the only correct mode for all supported firmware.
- Copyright year bump 2025 → 2026 is appropriate.

**Minor style nit:** The removal of `ivpu_fw_init_wa()` leaves a double blank line (line 348 in the original has `}` closing `ivpu_fw_release`, then two blank lines before `static int ivpu_fw_mem_init`). This is visible in the diff context. Linux kernel style prefers a single blank line between functions. Very minor, not a blocker.

**ivpu_jsm_msg.c changes:**
- Removes the early return guard:
  ```c
  if (IVPU_WA(disable_d0i3_msg))
      return 0;
  ```
  This means `ivpu_jsm_pwr_d0i3_enter()` will now always send the IPC message. This is correct — with the workaround removed, the D0i3 entry message should always be sent.

**vpu_boot_api.h changes:**
- `VPU_BOOT_API_VER_PATCH` bumped from 4 to 5. This is a documentation-only change to the API header (the patch version tracks header formatting/comment changes, not ABI changes), which is appropriate since the comment for `d0i3_delayed_entry` is being updated.
- The comment update adds a deprecation note:
  ```c
  * NOTE: This parameter is deprecated starting NPU50xx+. Bit 0 is now hardcoded to 1,
  * meaning CPU state save always requires IPC message on D0i3 entry flow.
  ```
  This is good documentation. Also fixes a minor formatting inconsistency (`Bit0:` → `Bit 0:`) for readability.

**Overall:** Clean patch, no functional or correctness issues. The only minor observation is the double blank line left after removing `ivpu_fw_init_wa()`, but that's trivial.

---
Generated by Claude Code Patch Reviewer

^ permalink raw reply	[flat|nested] 4+ messages in thread

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2026-05-26 12:55 [PATCH] accel/ivpu: Remove disable_d0i3_msg workaround Andrzej Kacprowski
2026-05-26 13:03 ` Wachowski, Karol
2026-05-27  4:51 ` Claude review: " Claude Code Review Bot
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