[PATCH] accel/ivpu: Fix swapped register names in pwr_island_drive functions

[PATCH] accel/ivpu: Fix swapped register names in pwr_island_drive functions

[Karol Wachowski]

pwr_island_drive_37xx and pwr_island_drive_40xx functions had incorrectly
swapped registers definitions. Bug is purely cosmetic as those registers
have exactly same offsets and layout in both 37XX and 40XX.

Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com>
---
 drivers/accel/ivpu/ivpu_hw_ip.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/accel/ivpu/ivpu_hw_ip.c b/drivers/accel/ivpu/ivpu_hw_ip.c
index 37f95a0551ed..81f0b1f8f5a6 100644
--- a/drivers/accel/ivpu/ivpu_hw_ip.c
+++ b/drivers/accel/ivpu/ivpu_hw_ip.c
@@ -308,26 +308,26 @@ static void pwr_island_trickle_drive_40xx(struct ivpu_device *vdev, bool enable)
 
 static void pwr_island_drive_37xx(struct ivpu_device *vdev, bool enable)
 {
-	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
 
 	if (enable)
-		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
+		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
 	else
-		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
+		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
 
-	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
+	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
 }
 
 static void pwr_island_drive_40xx(struct ivpu_device *vdev, bool enable)
 {
-	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
+	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
 
 	if (enable)
-		val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
+		val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
 	else
-		val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, MSS_CPU, val);
+		val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, CSS_CPU, val);
 
-	REGV_WR32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
+	REGV_WR32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0, val);
 }
 
 static void pwr_island_enable(struct ivpu_device *vdev)
-- 
2.43.0

Claude review: accel/ivpu: Fix swapped register names in pwr_island_drive functions

[Claude Code Review Bot]

Overall Series Review

Subject: accel/ivpu: Fix swapped register names in pwr_island_drive functions
Author: Karol Wachowski <karol.wachowski@linux.intel.com>
Patches: 1
Reviewed: 2026-04-23T08:38:04.112852

---

This is a single-patch fix for the Intel VPU (NPU) accelerator driver (`accel/ivpu`). The patch swaps register name definitions that were incorrectly used in the wrong hardware-generation-specific functions: `pwr_island_drive_37xx` was using `VPU_40XX_*` register names, and `pwr_island_drive_40xx` was using `VPU_37XX_*` register names.

As the commit message correctly states, this is a **purely cosmetic fix** — both register names resolve to the same offset (`0x00030024u`) and both field masks (`MSS_CPU` for 37xx, `CSS_CPU` for 40xx) resolve to `BIT_MASK(3)`. The generated code is binary-identical before and after this patch. The fix improves code correctness and readability by ensuring each function uses the register definitions matching its hardware generation.

**Verdict**: Straightforward and correct. No functional risk.

---
Generated by Claude Code Patch Reviewer

Claude review: accel/ivpu: Fix swapped register names in pwr_island_drive functions

[Claude Code Review Bot]

Patch Review

**Assessment: Correct, no issues.**

The fix is a clean symmetric swap. In `pwr_island_drive_37xx`:
```c
-	u32 val = REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0);
+	u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0);
```
and the field name changes from `CSS_CPU` to `MSS_CPU` (matching the 37xx header definition). In `pwr_island_drive_40xx`, the inverse swap is applied.

I verified in the register definition headers:
- `ivpu_hw_37xx_reg.h:98`: `VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0 = 0x00030024u` with `MSS_CPU_MASK = BIT_MASK(3)`
- `ivpu_hw_40xx_reg.h:107`: `VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0 = 0x00030024u` with `CSS_CPU_MASK = BIT_MASK(3)`

The `REG_SET_FLD` / `REG_CLR_FLD` macros in `ivpu_hw_reg_io.h` concatenate `REG##_##FLD##_MASK` to form the mask name, so the register name and field name must be from the same generation's header. Before this patch they happened to work only because the offsets and bit positions are identical across generations.

**Minor notes:**
- The commit message could mention a `Fixes:` tag pointing to the commit that introduced the bug, which helps stable-tree backport tracking. However, since the bug is cosmetic, this is not strictly necessary.
- No functional change — safe to apply as-is.

---
Generated by Claude Code Patch Reviewer