Claude review: drm/msm/a8xx: use pipe protect slot 15 for last-span-unbound feature

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Correct fix, but exposes a pre-existing design issue**

The change from `protect->count_max` to hardcoded `15`:
```c
-	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg);
+	a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg);
```

This is necessary because A810 sets `count_max=64` (for its 64 global protect slots), but pipe protect registers only have 16 slots (0-15). The existing X285/A840 coincidentally worked because their `count_max=15` happened to be the correct pipe slot.

**Observation**: After this patch, `count_max` for X285 (15) and A840 (15) is technically wrong — they have 52+ global protect entries but `count_max=15`, which would fail a `BUILD_BUG_ON(count > count_max)` check if one were added. The reason it works is that `__build_asserts()` only checks a660/a690/a730 protect tables, not X285/A840. Consider updating X285 and A840 to `count_max=64` as well for consistency, since the field now only serves the BUILD_BUG_ON purpose.

The fix itself is correct and matches the downstream driver behavior per the commit message.

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