Claude review: drm/msm/adreno: set cx_misc_mmio regardless of if platform has LLCC

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Patch Review

**Status: Mostly good, one concern**

This patch decouples `cx_misc_mmio` mapping from LLCC slice availability. The motivation is clear: Milos has no LLCC but still needs to access `cx_mem` for fuse reads, TCM retention control, etc. Previously, if LLCC slices were unavailable, `cx_misc_mmio` was overwritten with `ERR_PTR(-EINVAL)`.

The approach is to:
1. Move MMU500 detection and `cx_misc_mmio` mapping from `a6xx_llc_slices_init()` into `a6xx_gpu_init()`
2. Change the early-return guard in `a6xx_llc_activate()` and `a7xx_llc_activate()` from checking `cx_misc_mmio` to checking both LLC slices directly

**Concern**: After this patch, if `cx_misc_mmio` mapping fails (msm_ioremap returns ERR_PTR) but LLCC slices succeed, the LLC activate functions would proceed to dereference an invalid `cx_misc_mmio` pointer via `a6xx_cx_misc_write()`/`a6xx_cx_misc_rmw()`. In practice this is unlikely (a platform with LLCC would have cx_mem), but the original code was more defensive by using `cx_misc_mmio` validity as the gatekeeper. Consider adding a check for `IS_ERR_OR_NULL(a6xx_gpu->cx_misc_mmio)` in the activate paths, or at least in `a6xx_gpu_init()` after the mapping.

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