Claude review: drm/msm/adreno: add Adreno 810 GPU support

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Status: Mostly good, minor issues**

This is the main enablement patch adding the catalog entry, register lists, and helper function.

**Catalog entry** (`adreno_info` for chip_id `0x44010000`):
- Family `ADRENO_8XX_GEN1` — correct, this is the first GEN1 device
- Firmware `gen80300_*` — distinct from X285 (gen80100) and A840 (gen80200), no AQE firmware
- GMEM `SZ_512K + SZ_64K` = 576K — significantly smaller than X285 (21MB) and A840 (18MB), consistent with a mid-range part
- Quirks include `ADRENO_QUIRK_IFPC` but not `ADRENO_QUIRK_SOFTFUSE` — correct, uses regular efuse per the DTS
- Reuses `a840_gbif` for `.gbif_cx` — seems intentional
- `max_slices = 1` — simpler than X285 (4) and A840 (3)
- `gmu_chipid = 0x8030000` — the zero minor/revision fields are noted
- `preempt_record_size = 4558 * SZ_1K` — specific to this GPU

**Unused helper**: `adreno_is_a810()` is defined but never called in this series. While `adreno_is_a840()` and `adreno_is_x285()` have existing callers, adding an unused function is unnecessary — it can be added when actually needed.

**RSCC question**: The existing code at `a6xx_gmu.c:648` uses `adreno_is_a840()` to select `BIT(30)` vs `BIT(16)` for RSCC status polling. Does A810 need the `BIT(30)` path? This may be handled by the dependent RSCC offset fix series, but worth confirming.

**Register lists** look thorough:
- `a810_nonctxt_regs`: Well-commented entries for ECO controls and chicken bits
- `a810_protect_regs`: 47 entries with `DECLARE_ADRENO_PROTECT(a810_protect, 64)` — correctly sized
- `a810_ifpc_reglist_regs`: Includes all 64 `CP_PROTECT_GLOBAL` entries (0-63) for IFPC preservation
- `a810_dyn_pwrup_reglist_regs`: Includes the hardcoded `CP_PROTECT_PIPE(15)` matching the fix in patch 5

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Generated by Claude Code Patch Reviewer