[PATCH v2 0/4] Devicetree support for Glymur GPU

[PATCH v2 0/4] Devicetree support for Glymur GPU

[Akhil P Oommen]

This series adds the necessary Device Tree bits to enable GPU support
on the Glymur-based CRD devices. The Adreno X2-85 GPU present in Glymur
chipsets is based on the new Adreno A8x family of GPUs. It features a new
slice architecture with 4 slices, significantly higher bandwidth
throughput compared to mobile counterparts, raytracing support, and the
highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other
improvements.

This series includes patches that updates DT schema, add GPU SMMU &
GPU/GMU support. Keen-eyed readers may notice that the zap shader node
is missing. This is intentional: The Glymur-based laptop platforms
generally allow booting Linux at EL2 (yay!), which means the zap firmware
is not required here.

There is an update to the gxclkctl/drm drivers to properly support the IFPC
feature across all A8x GPUs. That series [1] is necessary to properly
support Glymur GPU:
[1] https://lore.kernel.org/lkml/20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com/

Just FYI, on top of the linux-next, I had to pick below series [2] to boot
the device properly. But it is unrelated to GPU or this series:
[2] https://lore.kernel.org/all/20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com/

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v2:
- Keep GPU/GMU enabled by default and drop the enablement patch (Konrad)
- Drop zap shader node from DT
- A new patch to update GPU SMMU dt schema.
- Adjust reg range in dt nodes to avoid overlap. 
- Removed cx_dbgc range as it is already stable across chipsets. This
  region is now part of kgsl_3d0_reg_memory range.
- Link to v1: https://lore.kernel.org/r/20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com

---
Akhil P Oommen (3):
      dt-bindings: display/msm: gpu: Document Adreno X2-185
      dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU
      arm64: dts: qcom: Add GPU support for Glymur

Rajendra Nayak (1):
      arm64: dts: qcom: glymur: Add GPU smmu node

 .../devicetree/bindings/display/msm/gpu.yaml       |   1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml        |   7 +-
 arch/arm64/boot/dts/qcom/glymur.dtsi               | 223 +++++++++++++++++++++
 3 files changed, 230 insertions(+), 1 deletion(-)
---
base-commit: c9bd03db3e792a99e9789fde20e91898e3a29e8a
change-id: 20260226-glymur-gpu-dt-339e5092606b
prerequisite-message-id: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com>
prerequisite-patch-id: f7ab29f2f0241b6536d3b0c0593f0baa0e435221
prerequisite-patch-id: 56c830b7718129323b006e492aed9822d7c30079

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>

[PATCH v2 1/4] dt-bindings: display/msm: gpu: Document Adreno X2-185

[Akhil P Oommen]

Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family.
It features a new slice architecture with 4 slices, significantly higher
bandwidth throughput compared to mobile counterparts, raytracing support,
and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among
other improvements. Update the dt bindings documentation to describe this
GPU.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/display/msm/gpu.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 04b2328903ca19d35096f79f3aa958371d46182c..bdc8e6fa53596269854540b30d7540a21e7dcce3 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -434,6 +434,7 @@ allOf:
               - qcom,adreno-43050a01
               - qcom,adreno-43050c01
               - qcom,adreno-43051401
+              - qcom,adreno-44070001
 
     then: # Starting with A6xx, the clocks are usually defined in the GMU node
       properties:

-- 
2.51.0

Re: [PATCH v2 1/4] dt-bindings: display/msm: gpu: Document Adreno X2-185

[Krzysztof Kozlowski]

On Fri, May 01, 2026 at 10:40:37PM +0530, Akhil P Oommen wrote:
> Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family.
> It features a new slice architecture with 4 slices, significantly higher
> bandwidth throughput compared to mobile counterparts, raytracing support,
> and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among
> other improvements. Update the dt bindings documentation to describe this
> GPU.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/display/msm/gpu.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH v2 1/4] dt-bindings: display/msm: gpu: Document Adreno X2-185

[Krzysztof Kozlowski]

On 03/05/2026 16:10, Krzysztof Kozlowski wrote:
> On Fri, May 01, 2026 at 10:40:37PM +0530, Akhil P Oommen wrote:
>> Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family.
>> It features a new slice architecture with 4 slices, significantly higher
>> bandwidth throughput compared to mobile counterparts, raytracing support,
>> and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among
>> other improvements. Update the dt bindings documentation to describe this
>> GPU.
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>>  Documentation/devicetree/bindings/display/msm/gpu.yaml | 1 +
>>  1 file changed, 1 insertion(+)
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

I was a bit too fast and did not notice that this is only one if out of
two required. Where are the constraints for the rest of flexible properties?

Best regards,
Krzysztof

Claude review: dt-bindings: display/msm: gpu: Document Adreno X2-185

[Claude Code Review Bot]

Patch Review

**Status: Looks good.**

This patch adds a single compatible string entry:

```
              - qcom,adreno-43051401
+              - qcom,adreno-44070001
```

The compatible string `qcom,adreno-44070001` follows the established naming convention of `qcom,adreno-XXYYYZZZ` where the hex value encodes the chip/core/major/minor IDs. It is placed in sorted order after the existing A430 family entries.

One minor note: the commit message says "Adreno X2-185" but the cover letter says "Adreno X2-85". The subject line also says "X2-185". It would be good to confirm which marketing name is correct — the cover letter and the commit messages disagree. If the cover letter's "X2-85" is the correct name, the commit message subject should be updated.

No other concerns.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v2 2/4] dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU

[Akhil P Oommen]

Add the interconnects property to the common SMMU properties and extend
the sm8750 clock description section to also cover Glymur since it uses
the same single "hlos" vote clock.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 06fb5c8e7547cb7a92823adc2772b94f747376a6..df67ab2aa715f81f5a10678b936558827c105bd9 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -243,6 +243,9 @@ properties:
     minItems: 1
     maxItems: 3
 
+  interconnects:
+    maxItems: 1
+
   nvidia,memory-controller:
     description: |
       A phandle to the memory controller on NVIDIA Tegra186 and later SoCs.
@@ -566,7 +569,9 @@ allOf:
       properties:
         compatible:
           items:
-            - const: qcom,sm8750-smmu-500
+            - enum:
+                - qcom,glymur-smmu-500
+                - qcom,sm8750-smmu-500
             - const: qcom,adreno-smmu
             - const: qcom,smmu-500
             - const: arm,mmu-500

-- 
2.51.0

Re: [PATCH v2 2/4] dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU

[Krzysztof Kozlowski]

On 01/05/2026 19:10, Akhil P Oommen wrote:
> Add the interconnects property to the common SMMU properties and extend

But why? And why SDX55 (or any other device) has it for example?

> the sm8750 clock description section to also cover Glymur since it uses
> the same single "hlos" vote clock.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---


Best regards,
Krzysztof

Claude review: dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU

[Claude Code Review Bot]

Patch Review

**Status: Minor observations.**

This patch does two things:

1. Adds an `interconnects` property to the common SMMU properties:

```
+  interconnects:
+    maxItems: 1
```

2. Extends the SM8750-specific compatible section to also cover Glymur:

```
-            - const: qcom,sm8750-smmu-500
+            - enum:
+                - qcom,glymur-smmu-500
+                - qcom,sm8750-smmu-500
```

**Observations:**

- The `interconnects` addition at the top-level of the SMMU schema is a global change — it allows `interconnects` for *all* ARM SMMU variants, not just the Glymur one. Looking at the existing kernel tree, no current `adreno_smmu` node (sm8550, sm8650) uses `interconnects`. This is presumably a new requirement for Glymur. The DT binding maintainers may want to confirm whether this should be constrained to specific compatible strings rather than being globally allowed. That said, `maxItems: 1` is reasonable and the property is well-understood in the DT ecosystem.

- The sm8750 section reuse is sensible since Glymur and SM8750 share the same GPU SMMU clock configuration (single "hlos" clock).

---

---
Generated by Claude Code Patch Reviewer

[PATCH v2 3/4] arm64: dts: qcom: glymur: Add GPU smmu node

[Akhil P Oommen]

From: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>

Add the nodes to describe the GPU SMMU node.

Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index ed9aac42fcbf3684773ae449ecbea4ca679691a5..93afc81698cb64232ac6b61754fc6f4c923e30c8 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3729,6 +3729,46 @@ gpucc: clock-controller@3d90000 {
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x40000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
+			clock-names = "hlos";
+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			interconnects = <&hsc_noc MASTER_GPU_TCU QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			dma-coherent;
+		};
+
 		ipcc: mailbox@3e04000 {
 			compatible = "qcom,glymur-ipcc", "qcom,ipcc";
 			reg = <0x0 0x03e04000 0x0 0x1000>;

-- 
2.51.0

Claude review: arm64: dts: qcom: glymur: Add GPU smmu node

[Claude Code Review Bot]

Patch Review

**Status: Looks good. Already reviewed by Konrad and Dmitry.**

This adds the `adreno_smmu` IOMMU node at `0x03da0000`:

```
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x40000>;
```

**Observations:**

- The compatible string chain is correct: SoC-specific, then adreno-specific, then generic SMMU-500 variants.
- **26 interrupts** with `#global-interrupts = <1>`, meaning 1 global + 25 context bank interrupts. This is one more context bank interrupt than sm8550/sm8650 (which have 24 context bank interrupts). This seems plausible for a newer/larger GPU but worth confirming.
- The `interconnects` property referencing `hsc_noc MASTER_GPU_TCU` is new compared to older SoCs — consistent with the binding change in patch 2.
- Single clock (`GPU_CC_GPU_SMMU_VOTE_CLK` / "hlos") matches the sm8750 binding pattern, which is simpler than sm8550's 4-clock setup. This reflects a newer SMMU integration.
- Address space is clean: SMMU at `0x03da0000` starts exactly where `cx_mem` ends (`0x03d9e000 + 0x2000 = 0x03da0000`).

No issues found.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v2 4/4] arm64: dts: qcom: Add GPU support for Glymur

[Akhil P Oommen]

The Adreno X2 series GPU present in Glymur SoC belongs to the A8x
family. It is a new HW IP with architectural improvements as well
as different set of hw configs like GMEM, num SPs, Caches sizes etc.

Add the GPU and GMU nodes to describe this hardware.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi | 183 +++++++++++++++++++++++++++++++++++
 1 file changed, 183 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 93afc81698cb64232ac6b61754fc6f4c923e30c8..e36910ed348c8054dcab546c0b3936d781b11e14 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3701,6 +3701,129 @@ hsc_noc: interconnect@2000000 {
 			#interconnect-cells = <2>;
 		};
 
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-44070001", "qcom,adreno";
+			reg = <0x0 0x03d00000 0x0 0x6c000>,
+			      <0x0 0x03d9e000 0x0 0x2000>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem";
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0 0x0>,
+				 <&adreno_smmu 1 0x0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+			#cooling-cells = <2>;
+
+			interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2-adreno",
+					     "operating-points-v2";
+
+				opp-310000000 {
+					opp-hz = /bits/ 64 <310000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-peak-kBps = <2136719>;
+					opp-supported-hw = <0xf>;
+					/* ACD is disabled */
+				};
+
+				opp-410000000 {
+					opp-hz = /bits/ 64 <410000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <6074219>;
+					opp-supported-hw = <0xf>;
+					/* ACD is disabled */
+				};
+
+				opp-572000000 {
+					opp-hz = /bits/ 64 <572000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <12449219>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0xe02d5ffd>;
+				};
+
+				opp-760000000 {
+					opp-hz = /bits/ 64 <760000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <12449219>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0xc0285ffd>;
+				};
+
+				opp-820000000 {
+					opp-hz = /bits/ 64 <820000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0xa82e5ffd>;
+				};
+
+				opp-915000000 {
+					opp-hz = /bits/ 64 <915000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882d5ffd>;
+				};
+
+				opp-1070000000 {
+					opp-hz = /bits/ 64 <1070000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882b5ffd>;
+				};
+
+				opp-1185000000 {
+					opp-hz = /bits/ 64 <1185000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882a5ffd>;
+				};
+
+				opp-1350000000 {
+					opp-hz = /bits/ 64 <1350000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882a5ffd>;
+				};
+
+				opp-1550000000 {
+					opp-hz = /bits/ 64 <1550000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0x7>;
+					qcom,opp-acd-level = <0xa8295ffd>;
+				};
+
+				opp-1700000000 {
+					opp-hz = /bits/ 64 <1700000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0x7>;
+					qcom,opp-acd-level = <0x88295ffd>;
+				};
+
+				opp-1850000000 {
+					opp-hz = /bits/ 64 <1850000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0x3>;
+					qcom,opp-acd-level = <0x88285ffd>;
+				};
+			};
+		};
+
 		gxclkctl: clock-controller@3d64000 {
 			compatible = "qcom,glymur-gxclkctl";
 			reg = <0x0 0x03d64000 0x0 0x6000>;
@@ -3712,6 +3835,66 @@ gxclkctl: clock-controller@3d64000 {
 			#power-domain-cells = <1>;
 		};
 
+		gmu: gmu@3d6c000 {
+			compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
+
+			reg = <0x0 0x03d6c000 0x0 0x32000>;
+			reg-names = "gmu";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi",
+					  "gmu";
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+				 <&gpucc GPU_CC_RSCC_HUB_AON_CLK>;
+			clock-names = "ahb",
+				      "gmu",
+				      "cxo",
+				      "memnoc",
+				      "hub",
+				      "rscc";
+
+			power-domains = <&gpucc GPU_CC_CX_GDSC>,
+					<&gxclkctl GX_CLKCTL_GX_GDSC>;
+			power-domain-names = "cx",
+					     "gx";
+
+			iommus = <&adreno_smmu 5 0x0>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-575000000 {
+					opp-hz = /bits/ 64 <575000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+
+				opp-700000000 {
+					opp-hz = /bits/ 64 <700000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-725000000 {
+					opp-hz = /bits/ 64 <725000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				};
+
+				opp-750000000 {
+					opp-hz = /bits/ 64 <750000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+				};
+			};
+		};
+
 		gpucc: clock-controller@3d90000 {
 			compatible = "qcom,glymur-gpucc";
 			reg = <0x0 0x03d90000 0x0 0x9800>;

-- 
2.51.0

Claude review: arm64: dts: qcom: Add GPU support for Glymur

[Claude Code Review Bot]

Patch Review

**Status: Mostly good, a few items to consider.**

This is the main patch, adding the GPU and GMU nodes with a 12-entry OPP table.

**GPU node:**

```
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-44070001", "qcom,adreno";
+			reg = <0x0 0x03d00000 0x0 0x6c000>,
+			      <0x0 0x03d9e000 0x0 0x2000>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem";
```

- The `kgsl_3d0_reg_memory` region is `0x6c000` bytes, larger than sm8550's `0x40000`. This is consistent with a newer, larger GPU IP block. The cover letter mentions it includes the `cx_dbgc` range that was previously separate.

**OPP table:**

```
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2-adreno",
+					     "operating-points-v2";
```

- Uses `operating-points-v2-adreno` dual-compatible, consistent with the pattern in sm8650 and hamoa (newer SoCs). This is correct for supporting the `opp-supported-hw` and `qcom,opp-acd-level` properties used by the adreno driver.

- The `opp-supported-hw` values form a clear speed-bin mask pattern: `0xf` (all bins) for lower frequencies, `0x7` (bins 0-2) for 1550-1700 MHz, and `0x3` (bins 0-1) for the top 1850 MHz. This is a reasonable binning scheme.

- The two lowest OPPs (310 MHz, 410 MHz) have `/* ACD is disabled */` comments instead of `qcom,opp-acd-level`. This is a reasonable pattern — ACD (Adaptive Clock Distribution) is typically not needed at low voltages/frequencies.

**GMU node:**

```
+		gmu: gmu@3d6c000 {
+			compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
```

- The GMU compatible `qcom,adreno-gmu-x285.1` follows the newer naming pattern (matching the marketing "X2-85" name more closely than the GPU chip ID).

- **6 clocks** vs 7 on sm8550/sm8650. Missing `axi` and `demet`, but adds `rscc`. This is a different clock topology — presumably the RSCC (Resource State Coordinator Controller) hub clock replaces or subsumes the demet clock on this platform, and the AXI path is handled differently. This should be fine as long as the GMU driver supports this configuration.

- The GMU `reg` is at `0x03d6c000` with size `0x32000`, which ends at `0x03d9e000` — exactly where `cx_mem` begins. Good, no overlap.

**Node ordering:**

The GPU node is placed before `gxclkctl` (at `0x3d64000`), and the GMU is placed after `gxclkctl` but before `gpucc` (at `0x3d90000`). The GPU node's address `0x3d00000` comes before `gxclkctl`'s `0x3d64000`, and the GMU at `0x3d6c000` comes after `gxclkctl`. This ordering follows the DT convention of sorting by unit address, which is correct.

**Minor observations:**

1. The GPU `reg` range (`0x03d00000` to `0x03d6c000`) overlaps with `gxclkctl` at `0x03d64000` size `0x6000` (ending at `0x03d6a000`). The GPU `kgsl_3d0_reg_memory` covers `0x03d00000 + 0x6c000 = 0x03d6c000`, so it includes the range `0x03d64000-0x03d6a000` which is also claimed by `gxclkctl`. This is likely intentional — the GPU register space is a large contiguous block and the clock controller within it is described as a separate device for the clock framework. This is a common pattern in Qualcomm SoCs (the gpucc at `0x3d90000` is similarly within the broader GPU register range on some platforms). But reviewers may want to double-check this is intended.

2. No `status = "disabled"` on the GPU/GMU/SMMU nodes. The cover letter explicitly says "Keep GPU/GMU enabled by default and drop the enablement patch (Konrad)" — this was a v2 change based on reviewer feedback, so this is intentional.

**No blocking issues found.**

---
Generated by Claude Code Patch Reviewer

Claude review: Devicetree support for Glymur GPU

[Claude Code Review Bot]

Overall Series Review

Subject: Devicetree support for Glymur GPU
Author: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patches: 8
Reviewed: 2026-05-05T09:19:36.214070

---

This is a well-structured 4-patch series adding Device Tree support for the Adreno X2-185 GPU on Qualcomm's Glymur SoC. The series follows the standard pattern: DT binding updates first (patches 1-2), then DTS additions (patches 3-4). The cover letter is clear and provides good context about the hardware, dependencies, and the intentional omission of the zap shader node.

The patches are generally clean and follow existing Qualcomm GPU DT patterns. Patch 3 already has Reviewed-by tags from Konrad Dybcio and Dmitry Baryshkov. Patch 4 has Konrad's Reviewed-by. A few observations worth noting are below, but nothing is a hard blocker.

**Overall: Looks reasonable for a DT series. Minor items to consider below.**

---

---
Generated by Claude Code Patch Reviewer