[PATCH v10 0/3] Panel Replay BW optimization

[PATCH v10 0/3] Panel Replay BW optimization

[Animesh Manna]

Unused bandwidth can be used by external display agents for Panel Replay
enabled DP panel during idleness with link on. This patch series
enabling the same.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (3):
  drm/display: Add drm helper to check pr optimization support
  drm/i915/display: Add hook to check optimization support for Intel
    platforms
  drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

 drivers/gpu/drm/display/drm_dp_tunnel.c       | 17 +++++++++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 18 +++++++++++++
 .../gpu/drm/i915/display/intel_dp_tunnel.h    |  6 +++++
 drivers/gpu/drm/i915/display/intel_psr.c      | 25 +++++++++++++++++--
 include/drm/display/drm_dp_tunnel.h           |  6 +++++
 6 files changed, 71 insertions(+), 2 deletions(-)

-- 
2.29.0

[PATCH v10 1/3] drm/display: Add drm helper to check pr optimization support

[Animesh Manna]

Add api to check panel replay optimization supported or not to
drm-core DP tunneling framework which can be used by other driver
as well.

v2: Split generic drm changes from Intel specific changes. [Jouni]

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Suggested-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/display/drm_dp_tunnel.c | 17 +++++++++++++++++
 include/drm/display/drm_dp_tunnel.h     |  6 ++++++
 2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/display/drm_dp_tunnel.c b/drivers/gpu/drm/display/drm_dp_tunnel.c
index 6519b4244728..08dc5d26b2c5 100644
--- a/drivers/gpu/drm/display/drm_dp_tunnel.c
+++ b/drivers/gpu/drm/display/drm_dp_tunnel.c
@@ -149,6 +149,7 @@ struct drm_dp_tunnel {
 	bool bw_alloc_enabled:1;
 	bool has_io_error:1;
 	bool destroyed:1;
+	bool pr_optimization_support:1;
 };
 
 struct drm_dp_tunnel_group_state;
@@ -508,6 +509,8 @@ create_tunnel(struct drm_dp_tunnel_mgr *mgr,
 
 	tunnel->bw_alloc_supported = tunnel_reg_bw_alloc_supported(regs);
 	tunnel->bw_alloc_enabled = tunnel_reg_bw_alloc_enabled(regs);
+	tunnel->pr_optimization_support = tunnel_reg(regs, DP_TUNNELING_CAPABILITIES) &
+					  DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT;
 
 	if (!add_tunnel_to_group(mgr, drv_group_id, tunnel)) {
 		kfree(tunnel);
@@ -1036,6 +1039,20 @@ bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel)
 }
 EXPORT_SYMBOL(drm_dp_tunnel_bw_alloc_is_enabled);
 
+/**
+ * drm_dp_tunnel_pr_optimization_supported - Query the PR BW optimization support
+ * @tunnel: Tunnel object
+ *
+ * Query if the PR BW optimization is supported for @tunnel.
+ *
+ * Returns %true if the PR BW optimiation is supported for @tunnel.
+ */
+bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return tunnel && tunnel->pr_optimization_support;
+}
+EXPORT_SYMBOL(drm_dp_tunnel_pr_optimization_supported);
+
 static int clear_bw_req_state(struct drm_dp_aux *aux)
 {
 	u8 bw_req_mask = DP_BW_REQUEST_SUCCEEDED | DP_BW_REQUEST_FAILED;
diff --git a/include/drm/display/drm_dp_tunnel.h b/include/drm/display/drm_dp_tunnel.h
index 87212c847915..4aa3ce9fd829 100644
--- a/include/drm/display/drm_dp_tunnel.h
+++ b/include/drm/display/drm_dp_tunnel.h
@@ -53,6 +53,7 @@ int drm_dp_tunnel_destroy(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_enable_bw_alloc(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_disable_bw_alloc(struct drm_dp_tunnel *tunnel);
 bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel *tunnel);
+bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw);
 int drm_dp_tunnel_get_allocated_bw(struct drm_dp_tunnel *tunnel);
 int drm_dp_tunnel_update_state(struct drm_dp_tunnel *tunnel);
@@ -140,6 +141,11 @@ static inline bool drm_dp_tunnel_bw_alloc_is_enabled(const struct drm_dp_tunnel
 	return false;
 }
 
+static inline bool drm_dp_tunnel_pr_optimization_supported(const struct drm_dp_tunnel *tunnel)
+{
+	return false;
+}
+
 static inline int
 drm_dp_tunnel_alloc_bw(struct drm_dp_tunnel *tunnel, int bw)
 {
-- 
2.29.0

Claude review: drm/display: Add drm helper to check pr optimization support

[Claude Code Review Bot]

Patch Review

This adds a `pr_optimization_support` field to the tunnel struct, reads it from `DP_TUNNELING_CAPABILITIES` DPCD register at tunnel creation, and exposes a query function.

**Minor issue — typo in kdoc:**
```
 * Returns %true if the PR BW optimiation is supported for @tunnel.
```
"optimiation" → "optimization"

**Observation — no update on hotplug/re-detect:** The `pr_optimization_support` flag is only set in `create_tunnel()`. Looking at `tunnel_info_changes_are_valid()`, changes to `bw_alloc_supported` are detected and flagged, but there's no equivalent check for `pr_optimization_support`. This is probably fine in practice since the tunneling capabilities register is unlikely to change at runtime without a full disconnect/reconnect (which would destroy and recreate the tunnel), but it's worth noting for consistency. Not a blocker.

**The stub for `CONFIG_DRM_DISPLAY_DP_TUNNEL=n` is correct** — returns false.

---
Generated by Claude Code Patch Reviewer

[PATCH v10 2/3] drm/i915/display: Add hook to check optimization support for Intel platforms

[Animesh Manna]

Add a hook that uses the drm core tunneling function to check
whether panel replay bandwidth optimization support is present.

v2: Move DISPLAY_VER() check to
intel_dp_tunnel_pr_optimization_supported(). [Jouni]

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dp_tunnel.h |  6 ++++++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
index 7363c9817297..11712a151f72 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
@@ -296,6 +296,24 @@ bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp)
 	return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp->tunnel);
 }
 
+/**
+ * intel_dp_tunnel_pr_optimization_supported - Query the PR BW optimization support
+ * @intel_dp: DP port object
+ *
+ * Query whether a DP tunnel supports the PR BW optimization.
+ *
+ * Returns %true if the BW allocation mode is supported on @intel_dp.
+ */
+bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (DISPLAY_VER(display) < 35)
+		return false;
+
+	return drm_dp_tunnel_pr_optimization_supported(intel_dp->tunnel);
+}
+
 /**
  * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a port
  * @intel_dp: DP port object
diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
index 10ab9eebcef6..8273e681a512 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
@@ -32,6 +32,7 @@ void intel_dp_tunnel_resume(struct intel_dp *intel_dp,
 void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);
 
 bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp);
+bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp);
 
 void
 intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state);
@@ -76,6 +77,11 @@ static inline bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp
 	return false;
 }
 
+static inline bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp *intel_dp)
+{
+	return false;
+}
+
 static inline void
 intel_dp_tunnel_atomic_cleanup_inherited_state(struct intel_atomic_state *state) {}
 
-- 
2.29.0

Claude review: drm/i915/display: Add hook to check optimization support for Intel platforms

[Claude Code Review Bot]

Patch Review

Wraps the drm core function with a `DISPLAY_VER(display) < 35` guard.

**Kdoc mismatch:**
```
 * Returns %true if the BW allocation mode is supported on @intel_dp.
```
This is copy-pasted from the BW allocation function — it should say "PR BW optimization" instead of "BW allocation mode". The function name and description mention PR optimization correctly, but the Returns line is wrong.

**DISPLAY_VER check:** Gating on display version >= 35 is reasonable as this is a new platform feature. The stub for `CONFIG_DRM_DISPLAY_DP_TUNNEL=n` is correct.

---
Generated by Claude Code Patch Reviewer

[PATCH v10 3/3] drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Animesh Manna]

Unused bandwidth can be used by external display agents for Panel Replay
enabled DP panel during idleness with link on. Enable source to replace
dummy data from the display with data from another agent by programming
TRANS_DP2_CTL [Panel Replay Tunneling Enable].

v2:
- Enable pr bw optimization along with panel replay enable. [Jani]

v3:
- Write TRANS_DP2_CTL once for both bw optimization and panel replay
enable. [Jani]

v4:
- Read DPCD once in init() and store in panel_replay_caps. [Jouni]

v5:
- Avoid reading DPCD for edp. [Jouni]
- Use drm_dp_dpcd_read_byte() and some cosmetic changes. [Jani]

v6:
- Extend the corresponding interface defined in drm_dp_tunnel.c
to query the Panel Replay optimization capability. [Imre]

v7:
- Clear TRANS_DP2_PR_TUNNELING_ENABLE if pr bw optimization
is not allowed. [Jouni]
- Move intel_dp_is_edp() check. [Jouni]

Bspec: 68920
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 25 +++++++++++++++++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4746e9ebd920..dada8dc27ea4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2263,6 +2263,7 @@
 #define TRANS_DP2_CTL(trans)			_MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B)
 #define  TRANS_DP2_128B132B_CHANNEL_CODING	REG_BIT(31)
 #define  TRANS_DP2_PANEL_REPLAY_ENABLE		REG_BIT(30)
+#define  TRANS_DP2_PR_TUNNELING_ENABLE		REG_BIT(26)
 #define  TRANS_DP2_DEBUG_ENABLE			REG_BIT(23)
 
 #define _TRANS_DP2_VFREQHIGH_A			0x600a4
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2f1b48cd8efd..0a7d08f71c16 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -44,6 +44,7 @@
 #include "intel_dmc.h"
 #include "intel_dp.h"
 #include "intel_dp_aux.h"
+#include "intel_dp_tunnel.h"
 #include "intel_dsb.h"
 #include "intel_frontbuffer.h"
 #include "intel_hdmi.h"
@@ -1031,11 +1032,27 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp)
 	return frames_before_su_entry;
 }
 
+static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp)
+{
+	if (intel_dp_is_edp(intel_dp))
+		return false;
+
+	if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
+		return false;
+
+	if (!intel_dp_tunnel_pr_optimization_supported(intel_dp))
+		return false;
+
+	return true;
+}
+
 static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 {
 	struct intel_display *display = to_intel_display(intel_dp);
 	struct intel_psr *psr = &intel_dp->psr;
 	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
+	u32 dp2_ctl_set = TRANS_DP2_PANEL_REPLAY_ENABLE;
+	u32 dp2_ctl_clear = 0;
 
 	if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) {
 		u32 val = psr->su_region_et_enabled ?
@@ -1048,12 +1065,16 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
 			       val);
 	}
 
+	if (intel_psr_allow_pr_bw_optimization(intel_dp))
+		dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE;
+	else
+		dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE;
+
 	intel_de_rmw(display,
 		     PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder),
 		     0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME);
 
-	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
-		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), dp2_ctl_clear, dp2_ctl_set);
 }
 
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
-- 
2.29.0

Claude review: drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling

[Claude Code Review Bot]

Patch Review

This is the main functional patch. The `intel_psr_allow_pr_bw_optimization()` helper is clean and correctly checks: not eDP, BW alloc enabled, and PR optimization supported.

**Functional concern — deactivation path does not clear `TRANS_DP2_PR_TUNNELING_ENABLE`:**

The activation in `dg2_activate_panel_replay()` sets or clears `TRANS_DP2_PR_TUNNELING_ENABLE` correctly:
```c
	if (intel_psr_allow_pr_bw_optimization(intel_dp))
		dp2_ctl_set |= TRANS_DP2_PR_TUNNELING_ENABLE;
	else
		dp2_ctl_clear = TRANS_DP2_PR_TUNNELING_ENABLE;
```

But the deactivation at `intel_psr.c:2281` only clears `TRANS_DP2_PANEL_REPLAY_ENABLE`:
```c
	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
		     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
```

This leaves `TRANS_DP2_PR_TUNNELING_ENABLE` set after Panel Replay is deactivated. This could cause the tunneling hardware to continue attempting BW optimization when PR is no longer active, which seems wrong. The deactivation should also clear `TRANS_DP2_PR_TUNNELING_ENABLE`:
```c
	intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
		     TRANS_DP2_PANEL_REPLAY_ENABLE | TRANS_DP2_PR_TUNNELING_ENABLE, 0);
```

Similarly, the `intel_psr_get_config()` readback at line 4290 only checks `TRANS_DP2_PANEL_REPLAY_ENABLE` — it may be worth reading back the tunneling bit as well for debug/state verification, though this is less critical.

**The register bit definition** (`REG_BIT(26)`) and placement is consistent with the existing definitions in `intel_display_regs.h`.

**Overall**, this is a well-structured series. The deactivation path issue should be fixed before merging.

---
Generated by Claude Code Patch Reviewer

Claude review: Panel Replay BW optimization

[Claude Code Review Bot]

Overall Series Review

Subject: Panel Replay BW optimization
Author: Animesh Manna <animesh.manna@intel.com>
Patches: 4
Reviewed: 2026-03-31T17:12:01.327977

---

This is a v10 series adding Panel Replay bandwidth optimization for DP 2.0 tunneling. The concept is straightforward: when a Panel Replay-enabled DP panel is idle (link on but no new frames), the unused bandwidth can be reclaimed by other USB4 agents. The implementation is clean, well-layered (drm core helper → Intel wrapper → PSR usage), and has received reviews from Jouni Högander and Arun R Murthy.

The series is mostly in good shape but has two issues worth addressing — one functional concern in the deactivation path and one minor documentation typo.

---
Generated by Claude Code Patch Reviewer

[PATCH v7 0/3] Panel Replay BW optimization

[Animesh Manna]

Unused bandwidth can be used by external display agents for Panel Replay
enabled DP panel during idleness with link on. This patch series
enabling the same.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Animesh Manna (3):
  drm/i915/display: Add drm helper to check pr optimization support
  drm/i915/display: Panel Replay BW optimization for DP2.0 tunneling
  drm/i915/display: Disable Panel Replay for DP-tunneling without
    optimization

 drivers/gpu/drm/display/drm_dp_tunnel.c       | 17 ++++++++++
 .../gpu/drm/i915/display/intel_display_regs.h |  1 +
 .../gpu/drm/i915/display/intel_dp_tunnel.c    | 14 +++++++++
 .../gpu/drm/i915/display/intel_dp_tunnel.h    |  6 ++++
 drivers/gpu/drm/i915/display/intel_psr.c      | 31 +++++++++++++++++--
 include/drm/display/drm_dp_tunnel.h           |  6 ++++
 6 files changed, 73 insertions(+), 2 deletions(-)

-- 
2.29.0

Claude review: Panel Replay BW optimization

[Claude Code Review Bot]

Overall Series Review

Subject: Panel Replay BW optimization
Author: Animesh Manna <animesh.manna@intel.com>
Patches: 13
Reviewed: 2026-03-13T14:30:26.626654

---

This is a v7 3-patch series adding Panel Replay bandwidth optimization support for DP 2.0 tunneling in the i915 display driver. The concept is straightforward: when a Panel Replay-enabled DP panel is idle with the link on, unused bandwidth can be reclaimed by external display agents (e.g., USB4 data). The series adds infrastructure to query the tunnel bridge's capability, programs the hardware register bit to enable it, and disables Panel Replay entirely when tunneling is active but the bridge doesn't support the optimization (per DP spec requirement).

The series is generally clean and well-structured for a v7. A few issues noted below, ranging from a doc typo to a potential concern about deactivation path completeness.

---
Generated by Claude Code Patch Reviewer