[PATCH v3 0/5] Devicetree support for Glymur GPU

[PATCH v3 0/5] Devicetree support for Glymur GPU

[Akhil P Oommen]

This series adds the necessary Device Tree bits to enable GPU support
on the Glymur-based CRD devices. The Adreno X2-85 GPU present in Glymur
chipsets is based on the new Adreno A8x family of GPUs. It features a new
slice architecture with 4 slices, significantly higher bandwidth
throughput compared to mobile counterparts, raytracing support, and the
highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other
improvements.

This series includes patches that updates DT schema, add GPU SMMU &
GPU/GMU support. Keen-eyed readers may notice that the zap shader node
is missing. This is intentional: The Glymur-based laptop platforms
generally allow booting Linux at EL2 (yay!), which means the zap firmware
is not required here.

There is an update to the gxclkctl/drm drivers to properly support the IFPC
feature across all A8x GPUs. That series [1] is necessary to properly
support Glymur GPU:
[1] https://lore.kernel.org/lkml/20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com/

Just FYI, on top of the linux-next, I had to pick below series [2] to boot
the device properly. But it is unrelated to GPU or this series:
[2] https://lore.kernel.org/all/20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com/

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v3:
- Add a new patch to fix RSCC base vaddr in drm-msm
- Remove interconnect property from adreno smmu dt and the binding doc
- Add a contrait in GPU binding doc to limit the reg entries for Glymur
  (Krzysztof)
- Link to v2: https://lore.kernel.org/r/20260501-glymur-gpu-dt-v2-0-2f128b5596bb@oss.qualcomm.com

Changes in v2:
- Keep GPU/GMU enabled by default and drop the enablement patch (Konrad)
- Drop zap shader node from DT
- A new patch to update GPU SMMU dt schema.
- Adjust reg range in dt nodes to avoid overlap. 
- Removed cx_dbgc range as it is already stable across chipsets. This
  region is now part of kgsl_3d0_reg_memory range.
- Link to v1: https://lore.kernel.org/r/20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com

---
Akhil P Oommen (4):
      drm/msm/a8xx: Fix RSCC offset
      dt-bindings: display/msm: gpu: Document Adreno X2-185
      dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU
      arm64: dts: qcom: Add GPU support for Glymur

Rajendra Nayak (1):
      arm64: dts: qcom: glymur: Add GPU smmu node

 .../devicetree/bindings/display/msm/gpu.yaml       |  17 ++
 .../devicetree/bindings/iommu/arm,smmu.yaml        |   4 +-
 arch/arm64/boot/dts/qcom/glymur.dtsi               | 221 +++++++++++++++++++++
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c              |   7 +-
 4 files changed, 247 insertions(+), 2 deletions(-)
---
base-commit: c9bd03db3e792a99e9789fde20e91898e3a29e8a
change-id: 20260226-glymur-gpu-dt-339e5092606b
prerequisite-message-id: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com>
prerequisite-patch-id: f7ab29f2f0241b6536d3b0c0593f0baa0e435221
prerequisite-patch-id: 56c830b7718129323b006e492aed9822d7c30079

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>

[PATCH v3 1/5] drm/msm/a8xx: Fix RSCC offset

[Akhil P Oommen]

In A8xx, the RSCC block is part of GPU's register space. Update the
virtual base address of rscc to point to the correct address.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 1b44b9e21ad8..cab4c46c6cf2 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2357,7 +2357,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
 			goto err_mmio;
 		}
 	} else if (adreno_is_a8xx(adreno_gpu)) {
-		gmu->rscc = gmu->mmio + 0x19000;
+		/*
+		 * On a8xx , RSCC lives at GPU base + 0x50000, which falls
+		 * inside the GPU's kgsl_3d0_reg_memory range rather than the
+		 * GMU's.
+		 */
+		gmu->rscc = gpu->mmio + 0x50000;
 	} else {
 		gmu->rscc = gmu->mmio + 0x23000;
 	}

-- 
2.51.0

Re: [PATCH v3 1/5] drm/msm/a8xx: Fix RSCC offset

[Akhil P Oommen]

On 5/12/2026 1:36 AM, Akhil P Oommen wrote:
> In A8xx, the RSCC block is part of GPU's register space. Update the
> virtual base address of rscc to point to the correct address.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>

Missed the Fixes tag:

Fixes: 50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x GMU")

-Akhil

> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 1b44b9e21ad8..cab4c46c6cf2 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -2357,7 +2357,12 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
>  			goto err_mmio;
>  		}
>  	} else if (adreno_is_a8xx(adreno_gpu)) {
> -		gmu->rscc = gmu->mmio + 0x19000;
> +		/*
> +		 * On a8xx , RSCC lives at GPU base + 0x50000, which falls
> +		 * inside the GPU's kgsl_3d0_reg_memory range rather than the
> +		 * GMU's.
> +		 */
> +		gmu->rscc = gpu->mmio + 0x50000;
>  	} else {
>  		gmu->rscc = gmu->mmio + 0x23000;
>  	}
> 

Claude review: drm/msm/a8xx: Fix RSCC offset

[Claude Code Review Bot]

Patch Review

**Change:** Switches `gmu->rscc` from `gmu->mmio + 0x19000` to `gpu->mmio + 0x50000` for all A8xx GPUs.

This is a correctness fix. The RSCC block on A8xx lives at GPU base + 0x50000 (physical 0x3d50000), inside the GPU's `kgsl_3d0_reg_memory` range, not inside the GMU's register space. The old offset 0x19000 from GMU base (0x3d6c000) would yield physical 0x3d85000 -- a completely different address.

I verified that `gpu->mmio` is initialized before `a6xx_gmu_init()` runs (set in `msm_gpu_init()` called via `adreno_gpu_init()` at `a6xx_gpu.c:2671`, before `a6xx_gmu_init()` at line 2692).

**Minor nit:** The comment has a double space:
```c
		 * On a8xx , RSCC lives at GPU base + 0x50000, which falls
```
Should be `On a8xx,` (no space before comma).

**Question:** This changes behavior for **all** `adreno_is_a8xx()` GPUs (both `ADRENO_8XX_GEN1` / a830 family and `ADRENO_8XX_GEN2` / a840 family). Was the previous offset (gmu->mmio + 0x19000) ever correct for any A8xx part, or was this always wrong? The commit message says "Fix RSCC offset" but doesn't clarify whether existing A8xx support was broken. If the sm8750 A8xx GPU was working before with the old offset, this needs more explanation. If no A8xx board was actually booting Linux before, then this is fine as a pre-emptive fix.

**Verdict:** The change itself is correct in structure (uses the right variable, proper scope). The commit message could mention whether this is a regression fix or a fix for code that was never actually exercised.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v3 2/5] dt-bindings: display/msm: gpu: Document Adreno X2-185

[Akhil P Oommen]

Adreno X2-185 GPU found in Glymur chipsets belongs to the A8x family.
It features a new slice architecture with 4 slices, significantly higher
bandwidth throughput compared to mobile counterparts, raytracing support,
and the highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among
other improvements. Update the dt bindings documentation to describe this
GPU.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/display/msm/gpu.yaml | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 04b2328903ca..e67cd708dda2 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -411,6 +411,22 @@ allOf:
         - clocks
         - clock-names
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,adreno-44070001
+    then:
+      properties:
+        reg:
+          minItems: 2
+          maxItems: 2
+
+        reg-names:
+          items:
+            - const: kgsl_3d0_reg_memory
+            - const: cx_mem
+
   - if:
       properties:
         compatible:
@@ -434,6 +450,7 @@ allOf:
               - qcom,adreno-43050a01
               - qcom,adreno-43050c01
               - qcom,adreno-43051401
+              - qcom,adreno-44070001
 
     then: # Starting with A6xx, the clocks are usually defined in the GMU node
       properties:

-- 
2.51.0

Claude review: dt-bindings: display/msm: gpu: Document Adreno X2-185

[Claude Code Review Bot]

Patch Review

**Change:** Adds `qcom,adreno-44070001` to the GPU DT binding with constraints for exactly 2 reg entries (`kgsl_3d0_reg_memory` and `cx_mem`).

The compatible string matches the chip ID in `a6xx_catalog.c:2113`. The reg constraint of exactly 2 entries (no `cx_dbgc`) is consistent with the cover letter's explanation that cx_dbgc is now part of kgsl_3d0_reg_memory range.

The patch also adds the compatible to the "Starting with A6xx, clocks are defined in GMU node" block, which correctly disables `clocks`/`clock-names` at the GPU node level.

**Observation:** The subject says "Adreno X2-185" but the cover letter says "Adreno X2-85". Minor inconsistency in the marketing name -- the actual chip ID (44070001) is consistent throughout. This may just be the official full name vs. shorthand.

**Verdict:** Looks correct.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v3 3/5] dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU

[Akhil P Oommen]

Add the interconnects property to the common SMMU properties and extend
the sm8750 clock description section to also cover Glymur since it uses
the same single "hlos" vote clock.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 06fb5c8e7547..b811ece722c9 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -566,7 +566,9 @@ allOf:
       properties:
         compatible:
           items:
-            - const: qcom,sm8750-smmu-500
+            - enum:
+                - qcom,glymur-smmu-500
+                - qcom,sm8750-smmu-500
             - const: qcom,adreno-smmu
             - const: qcom,smmu-500
             - const: arm,mmu-500

-- 
2.51.0

Claude review: dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU

[Claude Code Review Bot]

Patch Review

**Change:** Extends the `qcom,sm8750-smmu-500` binding block to also cover `qcom,glymur-smmu-500` by converting the `const` to an `enum`.

This makes sense -- Glymur uses the same single "hlos" vote clock as sm8750. The YAML change is structurally correct: replacing `- const: qcom,sm8750-smmu-500` with a 2-element enum preserving sort order.

**Observation:** The commit message says "Add the interconnects property to the common SMMU properties" but the diff doesn't add any interconnects property -- that was apparently dropped per the v3 changelog ("Remove interconnect property from adreno smmu dt and the binding doc"). The commit message needs updating to match the actual change.

**Verdict:** The code change is correct but the **commit message is stale/misleading** -- it describes v2 content that was removed. Should be updated to something like "Extend the sm8750 GPU SMMU clock constraints to also cover Glymur, which uses the same single 'hlos' vote clock."

---

---
Generated by Claude Code Patch Reviewer

[PATCH v3 4/5] arm64: dts: qcom: glymur: Add GPU smmu node

[Akhil P Oommen]

From: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>

Add the nodes to describe the GPU SMMU node.

Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi | 38 ++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index ed9aac42fcbf..5e76a0d53f01 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3729,6 +3729,44 @@ gpucc: clock-controller@3d90000 {
 			#power-domain-cells = <1>;
 		};
 
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x40000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <1>;
+			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>;
+			clock-names = "hlos";
+			power-domains = <&gpucc GPU_CC_CX_GDSC>;
+			dma-coherent;
+		};
+
 		ipcc: mailbox@3e04000 {
 			compatible = "qcom,glymur-ipcc", "qcom,ipcc";
 			reg = <0x0 0x03e04000 0x0 0x1000>;

-- 
2.51.0

Claude review: arm64: dts: qcom: glymur: Add GPU smmu node

[Claude Code Review Bot]

Patch Review

**Change:** Adds the `adreno_smmu: iommu@3da0000` node to glymur.dtsi.

The node follows the standard pattern for Qualcomm GPU SMMUs:
- Compatible: `"qcom,glymur-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"` (4-element chain as required by the binding)
- 1 global interrupt + 25 context bank interrupts (26 total, `#global-interrupts = <1>`)
- Single `hlos` clock from gpucc
- `power-domains` referencing CX GDSC
- `dma-coherent` present

The node is placed after `gpucc` and before `ipcc` -- address ordering is correct (0x3da0000 between 0x3d90000 and 0x3e04000).

**Verdict:** Looks clean. Already has Reviewed-by from Konrad and Dmitry.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v3 5/5] arm64: dts: qcom: Add GPU support for Glymur

[Akhil P Oommen]

The Adreno X2 series GPU present in Glymur SoC belongs to the A8x
family. It is a new HW IP with architectural improvements as well
as different set of hw configs like GMEM, num SPs, Caches sizes etc.

Add the GPU and GMU nodes to describe this hardware.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/glymur.dtsi | 183 +++++++++++++++++++++++++++++++++++
 1 file changed, 183 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index 5e76a0d53f01..01a2e32e503b 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -3701,6 +3701,129 @@ hsc_noc: interconnect@2000000 {
 			#interconnect-cells = <2>;
 		};
 
+		gpu: gpu@3d00000 {
+			compatible = "qcom,adreno-44070001", "qcom,adreno";
+			reg = <0x0 0x03d00000 0x0 0x6c000>,
+			      <0x0 0x03d9e000 0x0 0x2000>;
+			reg-names = "kgsl_3d0_reg_memory",
+				    "cx_mem";
+
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+			iommus = <&adreno_smmu 0 0x0>,
+				 <&adreno_smmu 1 0x0>;
+
+			operating-points-v2 = <&gpu_opp_table>;
+
+			qcom,gmu = <&gmu>;
+			#cooling-cells = <2>;
+
+			interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+			interconnect-names = "gfx-mem";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2-adreno",
+					     "operating-points-v2";
+
+				opp-310000000 {
+					opp-hz = /bits/ 64 <310000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+					opp-peak-kBps = <2136719>;
+					opp-supported-hw = <0xf>;
+					/* ACD is disabled */
+				};
+
+				opp-410000000 {
+					opp-hz = /bits/ 64 <410000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-peak-kBps = <6074219>;
+					opp-supported-hw = <0xf>;
+					/* ACD is disabled */
+				};
+
+				opp-572000000 {
+					opp-hz = /bits/ 64 <572000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-peak-kBps = <12449219>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0xe02d5ffd>;
+				};
+
+				opp-760000000 {
+					opp-hz = /bits/ 64 <760000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-peak-kBps = <12449219>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0xc0285ffd>;
+				};
+
+				opp-820000000 {
+					opp-hz = /bits/ 64 <820000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0xa82e5ffd>;
+				};
+
+				opp-915000000 {
+					opp-hz = /bits/ 64 <915000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882d5ffd>;
+				};
+
+				opp-1070000000 {
+					opp-hz = /bits/ 64 <1070000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882b5ffd>;
+				};
+
+				opp-1185000000 {
+					opp-hz = /bits/ 64 <1185000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+					opp-peak-kBps = <16500000>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882a5ffd>;
+				};
+
+				opp-1350000000 {
+					opp-hz = /bits/ 64 <1350000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0xf>;
+					qcom,opp-acd-level = <0x882a5ffd>;
+				};
+
+				opp-1550000000 {
+					opp-hz = /bits/ 64 <1550000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0x7>;
+					qcom,opp-acd-level = <0xa8295ffd>;
+				};
+
+				opp-1700000000 {
+					opp-hz = /bits/ 64 <1700000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0x7>;
+					qcom,opp-acd-level = <0x88295ffd>;
+				};
+
+				opp-1850000000 {
+					opp-hz = /bits/ 64 <1850000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+					opp-peak-kBps = <18597657>;
+					opp-supported-hw = <0x3>;
+					qcom,opp-acd-level = <0x88285ffd>;
+				};
+			};
+		};
+
 		gxclkctl: clock-controller@3d64000 {
 			compatible = "qcom,glymur-gxclkctl";
 			reg = <0x0 0x03d64000 0x0 0x6000>;
@@ -3712,6 +3835,66 @@ gxclkctl: clock-controller@3d64000 {
 			#power-domain-cells = <1>;
 		};
 
+		gmu: gmu@3d6c000 {
+			compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu";
+
+			reg = <0x0 0x03d6c000 0x0 0x32000>;
+			reg-names = "gmu";
+
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hfi",
+					  "gmu";
+
+			clocks = <&gpucc GPU_CC_AHB_CLK>,
+				 <&gpucc GPU_CC_CX_GMU_CLK>,
+				 <&gpucc GPU_CC_CXO_CLK>,
+				 <&gcc GCC_GPU_GEMNOC_GFX_CLK>,
+				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+				 <&gpucc GPU_CC_RSCC_HUB_AON_CLK>;
+			clock-names = "ahb",
+				      "gmu",
+				      "cxo",
+				      "memnoc",
+				      "hub",
+				      "rscc";
+
+			power-domains = <&gpucc GPU_CC_CX_GDSC>,
+					<&gxclkctl GX_CLKCTL_GX_GDSC>;
+			power-domain-names = "cx",
+					     "gx";
+
+			iommus = <&adreno_smmu 5 0x0>;
+
+			qcom,qmp = <&aoss_qmp>;
+
+			operating-points-v2 = <&gmu_opp_table>;
+
+			gmu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-575000000 {
+					opp-hz = /bits/ 64 <575000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+				};
+
+				opp-700000000 {
+					opp-hz = /bits/ 64 <700000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+				};
+
+				opp-725000000 {
+					opp-hz = /bits/ 64 <725000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+				};
+
+				opp-750000000 {
+					opp-hz = /bits/ 64 <750000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+				};
+			};
+		};
+
 		gpucc: clock-controller@3d90000 {
 			compatible = "qcom,glymur-gpucc";
 			reg = <0x0 0x03d90000 0x0 0x9800>;

-- 
2.51.0

Claude review: arm64: dts: qcom: Add GPU support for Glymur

[Claude Code Review Bot]

Patch Review

**Change:** Adds the `gpu@3d00000` and `gmu@3d6c000` nodes to glymur.dtsi.

**GPU node (`gpu@3d00000`):**
- Compatible: `"qcom,adreno-44070001", "qcom,adreno"` -- matches catalog
- reg: `kgsl_3d0_reg_memory` at 0x3d00000 size 0x6c000, `cx_mem` at 0x3d9e000 size 0x2000 -- matches the 2-reg constraint from patch 2
- The kgsl_3d0_reg_memory range (0x3d00000 - 0x3d6c000) encompasses the RSCC at 0x3d50000 (gpu base + 0x50000 from patch 1), which is consistent
- 12 OPP entries from 310MHz to 1850MHz, with ACD disabled on the two lowest frequencies
- The highest OPPs (1550/1700/1850 MHz) have progressively restricted `opp-supported-hw` masks (0x7, 0x7, 0x3), consistent with speedbin support in the catalog
- interconnects properly reference `hsc_noc` and `mc_virt`

**GMU node (`gmu@3d6c000`):**
- Compatible: `"qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"`
- reg: single "gmu" region at 0x3d6c000, size 0x32000
- 6 clocks including `rscc` clock -- note this is a new clock compared to some other GMU nodes
- Power domains: CX from gpucc, GX from gxclkctl
- 4 GMU OPP entries from 575MHz to 750MHz

**Node ordering:** `gpu@3d00000` is inserted before `gxclkctl@3d64000`, and `gmu@3d6c000` is inserted after `gxclkctl` and before `gpucc@3d90000`. This maintains ascending address order.

**Address overlap note:** The GPU kgsl_3d0_reg_memory range (0x3d00000-0x3d6c000) physically encompasses the gxclkctl range (0x3d64000-0x3d6a000). Similarly, the GMU range (0x3d6c000-0x3d9e000) encompasses gpucc (0x3d90000-0x3d99800). These overlaps are typical of Qualcomm SoCs where sub-blocks are carved from larger address regions and managed by different drivers. Not a problem.

**Verdict:** Looks correct and well-structured.

---

### Summary

The series is in good shape. Two items to address before merging:

1. **Patch 3**: The commit message is stale -- it references adding an `interconnects` property that was actually removed in v3. Needs a reword.
2. **Patch 1**: Minor cosmetic -- extra space before comma in the comment (`On a8xx ,`). Also could benefit from clarifying in the commit message whether this fixes a real regression on existing A8xx hardware or is fixing not-yet-exercised code.

---
Generated by Claude Code Patch Reviewer

Claude review: Devicetree support for Glymur GPU

[Claude Code Review Bot]

Overall Series Review

Subject: Devicetree support for Glymur GPU
Author: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patches: 7
Reviewed: 2026-05-16T14:42:41.960670

---

This is a v3 series adding Device Tree support for the Adreno X2-85 GPU (chip ID 0x44070001, family A8x Gen2) on the Qualcomm Glymur SoC. The series is well-structured: driver fix first (patch 1), then DT bindings (patches 2-3), then DT nodes (patches 4-5). The GPU and SMMU support in the kernel driver already exists (confirmed in `a6xx_catalog.c`), so this series is purely about wiring up the DT for a new board.

Overall the series looks **reasonable and close to mergeable**. The RSCC fix (patch 1) is a genuine bug fix affecting all A8xx GPUs, and the DT additions follow established patterns from sm8650/sm8750. A few observations below.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v4 0/6] Devicetree support for Glymur GPU

[Akhil P Oommen]

This series adds the necessary Device Tree bits to enable GPU support
on the Glymur-based CRD devices. The Adreno X2-85 GPU present in Glymur
chipsets is based on the new Adreno A8x family of GPUs. It features a new
slice architecture with 4 slices, significantly higher bandwidth
throughput compared to mobile counterparts, raytracing support, and the
highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other
improvements.

This series includes patches that updates DT schema, add GPU SMMU &
GPU/GMU support. Keen-eyed readers may notice that the zap shader node
is missing. This is intentional: The Glymur-based laptop platforms
generally allow booting Linux at EL2 (yay!), which means the zap firmware
is not required here.

There is an update to the gxclkctl/drm drivers to properly support the IFPC
feature across all A8x GPUs. That series [1] is necessary to properly
support Glymur GPU:
[1] https://lore.kernel.org/lkml/20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com/

Just FYI, on top of the linux-next, I had to pick below series [2] to boot
the device properly. But it is unrelated to GPU or this series:
[2] https://lore.kernel.org/all/20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com/

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v4:
- Add a new patch for passive cooling support
- Link to v3: https://lore.kernel.org/r/20260512-glymur-gpu-dt-v3-0-84232dc21c03@oss.qualcomm.com

Changes in v3:
- Add a new patch to fix RSCC base vaddr in drm-msm
- Remove interconnect property from adreno smmu dt and the binding doc
- Add a contrait in GPU binding doc to limit the reg entries for Glymur
  (Krzysztof)
- Link to v2: https://lore.kernel.org/r/20260501-glymur-gpu-dt-v2-0-2f128b5596bb@oss.qualcomm.com

Changes in v2:
- Keep GPU/GMU enabled by default and drop the enablement patch (Konrad)
- Drop zap shader node from DT
- A new patch to update GPU SMMU dt schema.
- Adjust reg range in dt nodes to avoid overlap. 
- Removed cx_dbgc range as it is already stable across chipsets. This
  region is now part of kgsl_3d0_reg_memory range.
- Link to v1: https://lore.kernel.org/r/20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com

---
Akhil P Oommen (4):
      drm/msm/a8xx: Fix RSCC offset
      dt-bindings: display/msm: gpu: Document Adreno X2-185
      dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU
      arm64: dts: qcom: Add GPU support for Glymur

Manaf Meethalavalappu Pallikunhi (1):
      arm64: dts: qcom: glymur: Add GPU cooling

Rajendra Nayak (1):
      arm64: dts: qcom: glymur: Add GPU smmu node

 .../devicetree/bindings/display/msm/gpu.yaml       |  17 +
 .../devicetree/bindings/iommu/arm,smmu.yaml        |   4 +-
 arch/arm64/boot/dts/qcom/glymur.dtsi               | 461 ++++++++++++++++++---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c              |   7 +-
 4 files changed, 431 insertions(+), 58 deletions(-)
---
base-commit: c9bd03db3e792a99e9789fde20e91898e3a29e8a
change-id: 20260226-glymur-gpu-dt-339e5092606b
prerequisite-message-id: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com>
prerequisite-patch-id: f7ab29f2f0241b6536d3b0c0593f0baa0e435221
prerequisite-patch-id: 56c830b7718129323b006e492aed9822d7c30079

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>

Claude review: Devicetree support for Glymur GPU

[Claude Code Review Bot]

Overall Series Review

Subject: Devicetree support for Glymur GPU
Author: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patches: 10
Reviewed: 2026-05-16T12:51:46.611657

---

This is a well-structured v4 series adding GPU (Adreno X2-185) device tree support for Qualcomm's Glymur SoC. It consists of a driver fix (RSCC offset), two binding updates, and three DTS patches (SMMU, GPU/GMU, and thermal cooling). The series is logically ordered with proper dependencies between patches. The driver fix (patch 1) is appropriately tagged with Fixes and should go to stable. The DT patches follow existing Qualcomm patterns. One minor comment typo in patch 1 and a few small observations below, but overall this series looks ready.

---

---
Generated by Claude Code Patch Reviewer

[PATCH v2 0/4] Devicetree support for Glymur GPU

[Akhil P Oommen]

This series adds the necessary Device Tree bits to enable GPU support
on the Glymur-based CRD devices. The Adreno X2-85 GPU present in Glymur
chipsets is based on the new Adreno A8x family of GPUs. It features a new
slice architecture with 4 slices, significantly higher bandwidth
throughput compared to mobile counterparts, raytracing support, and the
highest GPU Fmax seen so far on an Adreno GPU (1850 Mhz), among other
improvements.

This series includes patches that updates DT schema, add GPU SMMU &
GPU/GMU support. Keen-eyed readers may notice that the zap shader node
is missing. This is intentional: The Glymur-based laptop platforms
generally allow booting Linux at EL2 (yay!), which means the zap firmware
is not required here.

There is an update to the gxclkctl/drm drivers to properly support the IFPC
feature across all A8x GPUs. That series [1] is necessary to properly
support Glymur GPU:
[1] https://lore.kernel.org/lkml/20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com/

Just FYI, on top of the linux-next, I had to pick below series [2] to boot
the device properly. But it is unrelated to GPU or this series:
[2] https://lore.kernel.org/all/20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com/

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v2:
- Keep GPU/GMU enabled by default and drop the enablement patch (Konrad)
- Drop zap shader node from DT
- A new patch to update GPU SMMU dt schema.
- Adjust reg range in dt nodes to avoid overlap. 
- Removed cx_dbgc range as it is already stable across chipsets. This
  region is now part of kgsl_3d0_reg_memory range.
- Link to v1: https://lore.kernel.org/r/20260405-glymur-gpu-dt-v1-0-2135eb11c562@oss.qualcomm.com

---
Akhil P Oommen (3):
      dt-bindings: display/msm: gpu: Document Adreno X2-185
      dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU
      arm64: dts: qcom: Add GPU support for Glymur

Rajendra Nayak (1):
      arm64: dts: qcom: glymur: Add GPU smmu node

 .../devicetree/bindings/display/msm/gpu.yaml       |   1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml        |   7 +-
 arch/arm64/boot/dts/qcom/glymur.dtsi               | 223 +++++++++++++++++++++
 3 files changed, 230 insertions(+), 1 deletion(-)
---
base-commit: c9bd03db3e792a99e9789fde20e91898e3a29e8a
change-id: 20260226-glymur-gpu-dt-339e5092606b
prerequisite-message-id: <20260410-glymur_mmcc_dt_config_v2-v3-0-acce9d106e72@oss.qualcomm.com>
prerequisite-patch-id: f7ab29f2f0241b6536d3b0c0593f0baa0e435221
prerequisite-patch-id: 56c830b7718129323b006e492aed9822d7c30079

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>

Claude review: Devicetree support for Glymur GPU

[Claude Code Review Bot]

Overall Series Review

Subject: Devicetree support for Glymur GPU
Author: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patches: 8
Reviewed: 2026-05-05T09:19:36.214070

---

This is a well-structured 4-patch series adding Device Tree support for the Adreno X2-185 GPU on Qualcomm's Glymur SoC. The series follows the standard pattern: DT binding updates first (patches 1-2), then DTS additions (patches 3-4). The cover letter is clear and provides good context about the hardware, dependencies, and the intentional omission of the zap shader node.

The patches are generally clean and follow existing Qualcomm GPU DT patterns. Patch 3 already has Reviewed-by tags from Konrad Dybcio and Dmitry Baryshkov. Patch 4 has Konrad's Reviewed-by. A few observations worth noting are below, but nothing is a hard blocker.

**Overall: Looks reasonable for a DT series. Minor items to consider below.**

---

---
Generated by Claude Code Patch Reviewer