Claude review: dt-bindings: display: renesas, rzg2l-du: Add RZ/T2H and RZ/N2H support

Claude review: dt-bindings: display: renesas, rzg2l-du: Add RZ/T2H and RZ/N2H support

[Claude Code Review Bot]

Patch Review

**The compatible strings and fallback pattern look fine.** The RZ/N2H→RZ/T2H fallback follows the established pattern used by RZ/V2L→RZ/G2L and RZ/V2N→RZ/V2H.

**Issue 1 — Removing `resets` and `ports` from global required list:**

```yaml
 required:
   - compatible
   - reg
   - interrupts
   - clocks
   - clock-names
-  - resets
   - power-domains
-  - ports
   - renesas,vsps
```

Removing `resets` and `ports` from the global `required` and conditionally adding them back in the `else` clause is workable, but the `else` clause will match _any_ compatible that does NOT contain `renesas,r9a09g077-du`. This is fine today but could be fragile if another SoC is added that also lacks a reset or uses `port` instead of `ports`. A more robust pattern would be to add an explicit `if` for the existing SoCs that require `resets`/`ports` rather than relying on an `else` that implicitly covers all non-T2H variants.

Actually, looking more carefully, the `else` is tied to the `r9a09g077-du` conditional:

```yaml
  - if:
      properties:
        compatible:
          contains:
            const: renesas,r9a09g077-du
    then:
      properties:
        resets: false
      required:
        - port
    else:
      required:
        - resets
        - ports
```

This is technically correct — the `else` covers all non-RZ/T2H variants, re-requiring `resets` and `ports`. But note that `resets: false` in the `then` clause actively forbids the property, which is a strong statement. The cover letter says "the DU does not have a reset line" — if that's definitive, this is fine, but it means DT authors can't even include an empty/stub reset on T2H. Confirm this is the hardware intent.

**Issue 2 — `port` vs `ports` with single port:**

The patch adds a new `port` property alongside the existing `ports`:

```yaml
  port:
    $ref: /schemas/graph.yaml#/properties/port
    description: Single output port for single-output DU variants.
```

The existing DU variants already handle single-output configurations using `ports` with a single `port@0` child (see the r9a07g043u and r9a09g057 cases). Using a bare `port` instead of `ports` for T2H creates an inconsistency in the binding. Consider whether `ports` with a single `port@0` child would be more consistent with the existing binding structure. This is a DT binding convention question that the DT maintainers (Rob/Krzysztof) should weigh in on.

**Issue 3 — No RZ/T2H-specific port description in allOf:**

The existing `allOf` blocks describe what each port represents (e.g., "DPI", "DSI"). The T2H `then` clause only requires `port` but doesn't add a description for what the port represents (presumably DPI). Minor but worth adding for consistency.

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: renesas, rzg2l-du: Add RZ/T2H and RZ/N2H support

[Claude Code Review Bot]

Patch Review

**Status: Has issues.**

The compatible string additions and the RZ/N2H fallback to RZ/T2H look correct:

```yaml
+          - renesas,r9a09g077-du # RZ/T2H
      - items:
+          - const: renesas,r9a09g087-du # RZ/N2H
+          - const: renesas,r9a09g077-du # RZ/T2H fallback
```

**Issue 1 — `resets` removal from global `required` plus if/else pattern:**

The patch removes `resets` from the global required list:

```yaml
-  - resets
```

And then adds an if/else block to conditionally require it:

```yaml
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g077-du
+    then:
+      properties:
+        resets: false
+    else:
+      required:
+        - resets
```

The `else` clause applies to every `allOf` entry that **doesn't** match the `if`. In a JSON Schema `allOf` list, each `if/then/else` item is evaluated independently. Since this is its own standalone item in the `allOf` array, the `else` branch should correctly require `resets` for all non-RZ/T2H compatibles. However, this pattern is unusual in DT bindings — most schemas simply list conditional requirements via `if/then` without `else`. It works, but a reviewer may ask whether it would be clearer to keep `resets` in the global `required` list and only use `if/then` to mark `resets: false` for RZ/T2H, since the `else` with `required: [resets]` is redundant with having it in the global list. Worth checking whether the dt-bindings maintainers prefer one style or the other.

**Issue 2 — port@1 constraint scope:** The patch groups `r9a09g077-du` (RZ/T2H) with `r9a07g043u-du` (RZ/G2UL) in the existing `if` block for single-port-only SoCs:

```yaml
          contains:
-            const: renesas,r9a07g043u-du
+            enum:
+              - renesas,r9a07g043u-du
+              - renesas,r9a09g077-du
```

This correctly constrains RZ/T2H to port@0 only and inherits the `port@1: false` from patch 1. This is appropriate since RZ/T2H has only a DPI output.

---
Generated by Claude Code Patch Reviewer

[PATCH v4 0/5] Add DU support for RZ/T2H and RZ/N2H SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This series adds support for the Display Unit (DU) on the RZ/T2H
and RZ/N2H (R9A09G087) SoCs. The DU on these platforms is
functionally similar to the RZ/G2UL DU but includes some SoC
specific differences such as a single output port and explicit
DPI output enable control. The series includes the following
changes:
1. Add device tree bindings for the RZ/T2H and RZ/N2H DU variants,
   including a new compatible string.
2. Make the DU reset control optional to allow probing on RZ/T2H
   where the DU does not have a reset line.
3. Move pixel clock validation logic to per-SoC constraints in
   rzg2l_du_device_info to accommodate different clock limits
   across SoCs.
4. Implement support for the RZ/T2H DU variant in the driver,
   including handling of the DPI output enable signal.

Patches are rebased on next-20260519 and apply on drm-next.

v3->v4:
- Added Acked-by tag from Rob for patch #1
- Added Reviewed-by tag from Rob for patches #2
- Dropped per pad limits in patch #4 and added
  a check to return early if the output is not DPAD0,
  as the clock limits only apply to that output.
- Updated commit message in patch #4

v2->v3:
- Rebased on latest next-20260508.
- Included Tommaso's patch to refuse port@1 for RZ/G2UL, which was
  previously in a separate series.
- Moved clock limits from device_info to output_routing to allow
  per-output constraints.
- Updated commit message for patch#4

v1->v2:
- Dropped the "port" property in favor of "ports" with a single port@0
  child, to align with the existing RZ/G2L bindings and simplify the
  device tree structure.
- Updated the commit message to reflect the change from "port" to "ports".
- Dropped storing info pointer in struct rzg2l_du_encoder as it's not
  needed.
- Add Reviewed-by tags from Laurent for patches 2-4.
- Rebase on latest next-20260507.

Cheers,
Prabhakar

Lad Prabhakar (4):
  dt-bindings: display: renesas,rzg2l-du: Add RZ/T2H and RZ/N2H support
  drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support
  drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits
  drm: renesas: rz-du: Add support for RZ/T2H SoC

Tommaso Merciai (1):
  dt-bindings: display: renesas,rzg2l-du: Refuse port@1 for RZ/G2UL

 .../bindings/display/renesas,rzg2l-du.yaml    | 21 +++++++++++++++++--
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c |  9 ++++++--
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  | 20 +++++++++++++++++-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  | 14 +++++++++++++
 .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c  |  9 +++++++-
 5 files changed, 67 insertions(+), 6 deletions(-)

-- 
2.54.0

[PATCH v4 1/5] dt-bindings: display: renesas, rzg2l-du: Refuse port@1 for RZ/G2UL

[Prabhakar]

From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

The RZ/G2UL DU supports only a single port@0 DPI. Explicitly refuse
port@1 in the ports node.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
- Added Acked-by tag from Rob.

v3:
- Was orignally part of separate series [0]
[0] https://lore.kernel.org/all/d1e0d4e0fe74e60345a3d043fb4f9128c1057638.1778141145.git.tommaso.merciai.xr@bp.renesas.com/
---
 Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 2cc66dcef870..5add3b832eab 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -102,6 +102,7 @@ allOf:
           properties:
             port@0:
               description: DPI
+            port@1: false
 
           required:
             - port@0
-- 
2.54.0

[PATCH v4 2/5] dt-bindings: display: renesas, rzg2l-du: Add RZ/T2H and RZ/N2H support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the Display Unit (DU) support for the RZ/T2H and RZ/N2H SoCs.

The DU block on RZ/T2H is functionally equivalent to the RZ/G2UL DU and
supports the DPI interface, but includes SoC-specific register differences
and has no reset control. Add a dedicated compatible string to represent
this variant and update the allOf constraints accordingly.

As the DU implementation on RZ/N2H matches RZ/T2H, describe it using an
RZ/N2H specific compatible string with the RZ/T2H compatible as fallback.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
v3->v4:
- Added RB tag from Rob.

v2->v3:
- No change

v1->v2:
- Dropped the "port" property in favor of "ports" with a single port@0
  child, to align with the existing RZ/G2L bindings and simplify the
  device tree structure.
- Updated the commit message to reflect the change from "port" to "ports".
- Dropped RB tag from Rob due to above changes.
---
 .../bindings/display/renesas,rzg2l-du.yaml    | 20 +++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
index 5add3b832eab..7c84a9ecc7a7 100644
--- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml
@@ -21,6 +21,7 @@ properties:
           - renesas,r9a07g043u-du # RZ/G2UL
           - renesas,r9a07g044-du # RZ/G2{L,LC}
           - renesas,r9a09g057-du # RZ/V2H(P)
+          - renesas,r9a09g077-du # RZ/T2H
       - items:
           - enum:
               - renesas,r9a07g054-du    # RZ/V2L
@@ -28,6 +29,9 @@ properties:
       - items:
           - const: renesas,r9a09g056-du # RZ/V2N
           - const: renesas,r9a09g057-du # RZ/V2H(P) fallback
+      - items:
+          - const: renesas,r9a09g087-du # RZ/N2H
+          - const: renesas,r9a09g077-du # RZ/T2H fallback
 
   reg:
     maxItems: 1
@@ -83,7 +87,6 @@ required:
   - interrupts
   - clocks
   - clock-names
-  - resets
   - power-domains
   - ports
   - renesas,vsps
@@ -95,7 +98,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: renesas,r9a07g043u-du
+            enum:
+              - renesas,r9a07g043u-du
+              - renesas,r9a09g077-du
     then:
       properties:
         ports:
@@ -138,6 +143,17 @@ allOf:
 
           required:
             - port@0
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g077-du
+    then:
+      properties:
+        resets: false
+    else:
+      required:
+        - resets
 
 examples:
   # RZ/G2L DU
-- 
2.54.0

[PATCH v4 3/5] drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Update the DU CRTC initialisation to request the reset control using
devm_reset_control_get_optional_shared(). On RZ/T2H SoCs the DU block does
not expose a reset line, and treating the reset as mandatory prevents the
driver from probing on those platforms.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v2->v4:
- No change

v1->v2:
- Added Reviewed-by tag from Laurent Pinchart.
---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
index 26b95153ce88..48065f4952a3 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
@@ -380,7 +380,7 @@ int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu)
 	struct drm_plane *primary;
 	int ret;
 
-	rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL);
+	rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, NULL);
 	if (IS_ERR(rcrtc->rstc)) {
 		dev_err(rcdu->dev, "can't get cpg reset\n");
 		return PTR_ERR(rcrtc->rstc);
-- 
2.54.0

[PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Move pixel clock validation from a fixed encoder check to per SoC
constraints stored in rzg2l_du_device_info.

Pixel clock limits differ across SoCs in the RZ DU family and cannot be
expressed by a single shared rule. For example, RZ/G2UL and RZ/G2L limit
the DPAD0 pixel clock to a narrow window, while other SoCs such as
RZ/T2H require a wider operating range.

Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to
describe the supported pixel clock range for each SoC. Update
rzg2l_du_encoder_mode_valid() to check these bounds when evaluating
DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls
below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max.

Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and
RZ/G2L (R9A07G044) variants to a minimum of 20875 kHz and a maximum of
83500 kHz.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4:
- Dropped per pad limits
- Updated commit message to reflect the change in approach.

v2->v3:
- Moved clock limits from device_info to output_routing to allow
  per-output constraints.
- Updated commit message to reflect the change in approach.

v1->v2:
- Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed.
---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c     | 6 +++++-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h     | 4 ++++
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++-
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
index 0fef33a5a089..1e4b9f38c55b 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
@@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
 			.port = 0,
 		},
 	},
+	.mode_clock_min = 20875,
+	.mode_clock_max = 83500,
 };
 
 static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
@@ -48,7 +50,9 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
 			.possible_outputs = BIT(0),
 			.port = 1,
 		}
-	}
+	},
+	.mode_clock_min = 20875,
+	.mode_clock_max = 83500,
 };
 
 static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index 58806c2a8f2b..885558eb9547 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -44,10 +44,14 @@ struct rzg2l_du_output_routing {
  * struct rzg2l_du_device_info - DU model-specific information
  * @channels_mask: bit mask of available DU channels
  * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*)
+ * @mode_clock_min: minimum pixel clock in kHz
+ * @mode_clock_max: maximum pixel clock in kHz
  */
 struct rzg2l_du_device_info {
 	unsigned int channels_mask;
 	struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
+	u32 mode_clock_min;
+	u32 mode_clock_max;
 };
 
 #define RZG2L_DU_MAX_CRTCS		1
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
index 0e567b57a408..56220139a149 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
@@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
 			    const struct drm_display_mode *mode)
 {
 	struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
+	struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
+	const struct rzg2l_du_device_info *info = rcdu->info;
 
-	if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
+	if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
+		return MODE_OK;
+
+	if (info->mode_clock_min && mode->clock < info->mode_clock_min)
+		return MODE_CLOCK_LOW;
+	if (info->mode_clock_max && mode->clock > info->mode_clock_max)
 		return MODE_CLOCK_HIGH;
 
 	return MODE_OK;
-- 
2.54.0

[PATCH v4 5/5] drm: renesas: rz-du: Add support for RZ/T2H SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The RZ/T2H (R9A09G077) SoC includes a DU with a DPI interface,
supporting resolutions up to WXGA with two RPFs for layer blending.
Unlike earlier RZ/G2L SoCs, RZ/T2H requires explicit assertion of a
DPI output-enable signal (DU_MCR0_DPI_EN) during CRTC startup.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
---
v3->v4:
- Dropped per pad limits

v2->v3:
- Moved clock limits from device_info to output_routing to allow
  per-output constraints.

v1->v2:
- Added Reviewed-by tag from Laurent Pinchart.
---
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c |  7 ++++++-
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c  | 14 ++++++++++++++
 drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  | 10 ++++++++++
 3 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
index 48065f4952a3..d0f01aa642a7 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c
@@ -28,6 +28,7 @@
 #include "rzg2l_du_vsp.h"
 
 #define DU_MCR0			0x00
+#define DU_MCR0_DPI_EN		BIT(0)
 #define DU_MCR0_DI_EN		BIT(8)
 
 #define DU_DITR0		0x10
@@ -217,8 +218,12 @@ static void rzg2l_du_crtc_put(struct rzg2l_du_crtc *rcrtc)
 static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start)
 {
 	struct rzg2l_du_device *rcdu = rcrtc->dev;
+	u32 val = DU_MCR0_DI_EN;
 
-	writel(start ? DU_MCR0_DI_EN : 0, rcdu->mmio + DU_MCR0);
+	if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE))
+		val |= DU_MCR0_DPI_EN;
+
+	writel(start ? val : 0, rcdu->mmio + DU_MCR0);
 }
 
 static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc)
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
index 1e4b9f38c55b..3d13f61d3c97 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
@@ -65,10 +65,24 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = {
 	},
 };
 
+static const struct rzg2l_du_device_info rzg2l_du_r9a09g077_info = {
+	.channels_mask = BIT(0),
+	.routes = {
+		[RZG2L_DU_OUTPUT_DPAD0] = {
+			.possible_outputs = BIT(0),
+			.port = 0,
+		},
+	},
+	.features = RZG2L_DU_FEATURE_DPIO_OE,
+	.mode_clock_min = 5000,
+	.mode_clock_max = 100000,
+};
+
 static const struct of_device_id rzg2l_du_of_table[] = {
 	{ .compatible = "renesas,r9a07g043u-du", .data = &rzg2l_du_r9a07g043u_info },
 	{ .compatible = "renesas,r9a07g044-du", .data = &rzg2l_du_r9a07g044_info },
 	{ .compatible = "renesas,r9a09g057-du", .data = &rzg2l_du_r9a09g057_info },
+	{ .compatible = "renesas,r9a09g077-du", .data = &rzg2l_du_r9a09g077_info },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
index 885558eb9547..baf076d69cda 100644
--- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
+++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
@@ -20,6 +20,8 @@
 struct device;
 struct drm_property;
 
+#define RZG2L_DU_FEATURE_DPIO_OE	BIT(0)	/* Has DPIO output enable control */
+
 enum rzg2l_du_output {
 	RZG2L_DU_OUTPUT_DSI0,
 	RZG2L_DU_OUTPUT_DPAD0,
@@ -46,12 +48,14 @@ struct rzg2l_du_output_routing {
  * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*)
  * @mode_clock_min: minimum pixel clock in kHz
  * @mode_clock_max: maximum pixel clock in kHz
+ * @features: device features (RZG2L_DU_FEATURE_*)
  */
 struct rzg2l_du_device_info {
 	unsigned int channels_mask;
 	struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
 	u32 mode_clock_min;
 	u32 mode_clock_max;
+	unsigned int features;
 };
 
 #define RZG2L_DU_MAX_CRTCS		1
@@ -77,6 +81,12 @@ static inline struct rzg2l_du_device *to_rzg2l_du_device(struct drm_device *dev)
 	return container_of(dev, struct rzg2l_du_device, ddev);
 }
 
+static inline bool rzg2l_du_has(struct rzg2l_du_device *rcdu,
+				unsigned int feature)
+{
+	return rcdu->info->features & feature;
+}
+
 const char *rzg2l_du_output_name(enum rzg2l_du_output output);
 
 #endif /* __RZG2L_DU_DRV_H__ */
-- 
2.54.0

RE: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Biju Das]

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 19 May 2026 17:08
> Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Move pixel clock validation from a fixed encoder check to per SoC constraints stored in
> rzg2l_du_device_info.
> 
> Pixel clock limits differ across SoCs in the RZ DU family and cannot be expressed by a single shared
> rule. For example, RZ/G2UL and RZ/G2L limit the DPAD0 pixel clock to a narrow window, while other SoCs
> such as RZ/T2H require a wider operating range.
> 
> Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to describe the supported pixel
> clock range for each SoC. Update
> rzg2l_du_encoder_mode_valid() to check these bounds when evaluating
> DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls below mode_clock_min and
> MODE_CLOCK_HIGH when it exceeds mode_clock_max.
> 
> Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and RZ/G2L (R9A07G044) variants to a
> minimum of 20875 kHz and a maximum of
> 83500 kHz.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3->v4:
> - Dropped per pad limits
> - Updated commit message to reflect the change in approach.
> 
> v2->v3:
> - Moved clock limits from device_info to output_routing to allow
>   per-output constraints.
> - Updated commit message to reflect the change in approach.
> 
> v1->v2:
> - Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed.
> ---
>  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c     | 6 +++++-
>  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h     | 4 ++++
>  drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++-
>  3 files changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-
> du/rzg2l_du_drv.c
> index 0fef33a5a089..1e4b9f38c55b 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
>  			.port = 0,
>  		},
>  	},
> +	.mode_clock_min = 20875,
> +	.mode_clock_max = 83500,
>  };
> 
>  static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { @@ -48,7 +50,9 @@ static const
> struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
>  			.possible_outputs = BIT(0),
>  			.port = 1,
>  		}
> -	}
> +	},
> +	.mode_clock_min = 20875,
> +	.mode_clock_max = 83500,
>  };
> 
>  static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = { diff --git
> a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> index 58806c2a8f2b..885558eb9547 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing {
>   * struct rzg2l_du_device_info - DU model-specific information
>   * @channels_mask: bit mask of available DU channels
>   * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*)
> + * @mode_clock_min: minimum pixel clock in kHz
> + * @mode_clock_max: maximum pixel clock in kHz
>   */
>  struct rzg2l_du_device_info {
>  	unsigned int channels_mask;
>  	struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
> +	u32 mode_clock_min;
> +	u32 mode_clock_max;
>  };
> 
>  #define RZG2L_DU_MAX_CRTCS		1
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-
> du/rzg2l_du_encoder.c
> index 0e567b57a408..56220139a149 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
>  			    const struct drm_display_mode *mode)  {
>  	struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
> +	struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
> +	const struct rzg2l_du_device_info *info = rcdu->info;
> 
> -	if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
> +	if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
> +		return MODE_OK;
> +
> +	if (info->mode_clock_min && mode->clock < info->mode_clock_min)

I will avoid checking the first part as it is mandatory for SoCs with DPI support
and DPI check above make sure that this part of the code is reachable only for DPI
output.

> +		return MODE_CLOCK_LOW;
> +	if (info->mode_clock_max && mode->clock > info->mode_clock_max)

Same here. 

Cheers,
Biju

>  		return MODE_CLOCK_HIGH;
> 
>  	return MODE_OK;
> --
> 2.54.0

Re: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Lad, Prabhakar]

Hi Biju,

Thank you for the review.

On Wed, May 20, 2026 at 6:36 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 19 May 2026 17:08
> > Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Move pixel clock validation from a fixed encoder check to per SoC constraints stored in
> > rzg2l_du_device_info.
> >
> > Pixel clock limits differ across SoCs in the RZ DU family and cannot be expressed by a single shared
> > rule. For example, RZ/G2UL and RZ/G2L limit the DPAD0 pixel clock to a narrow window, while other SoCs
> > such as RZ/T2H require a wider operating range.
> >
> > Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to describe the supported pixel
> > clock range for each SoC. Update
> > rzg2l_du_encoder_mode_valid() to check these bounds when evaluating
> > DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls below mode_clock_min and
> > MODE_CLOCK_HIGH when it exceeds mode_clock_max.
> >
> > Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U) and RZ/G2L (R9A07G044) variants to a
> > minimum of 20875 kHz and a maximum of
> > 83500 kHz.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3->v4:
> > - Dropped per pad limits
> > - Updated commit message to reflect the change in approach.
> >
> > v2->v3:
> > - Moved clock limits from device_info to output_routing to allow
> >   per-output constraints.
> > - Updated commit message to reflect the change in approach.
> >
> > v1->v2:
> > - Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed.
> > ---
> >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c     | 6 +++++-
> >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h     | 4 ++++
> >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++-
> >  3 files changed, 17 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-
> > du/rzg2l_du_drv.c
> > index 0fef33a5a089..1e4b9f38c55b 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
> >                       .port = 0,
> >               },
> >       },
> > +     .mode_clock_min = 20875,
> > +     .mode_clock_max = 83500,
> >  };
> >
> >  static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { @@ -48,7 +50,9 @@ static const
> > struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> >                       .possible_outputs = BIT(0),
> >                       .port = 1,
> >               }
> > -     }
> > +     },
> > +     .mode_clock_min = 20875,
> > +     .mode_clock_max = 83500,
> >  };
> >
> >  static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info = { diff --git
> > a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > index 58806c2a8f2b..885558eb9547 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing {
> >   * struct rzg2l_du_device_info - DU model-specific information
> >   * @channels_mask: bit mask of available DU channels
> >   * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*)
> > + * @mode_clock_min: minimum pixel clock in kHz
> > + * @mode_clock_max: maximum pixel clock in kHz
> >   */
> >  struct rzg2l_du_device_info {
> >       unsigned int channels_mask;
> >       struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
> > +     u32 mode_clock_min;
> > +     u32 mode_clock_max;
> >  };
> >
> >  #define RZG2L_DU_MAX_CRTCS           1
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-
> > du/rzg2l_du_encoder.c
> > index 0e567b57a408..56220139a149 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
> >                           const struct drm_display_mode *mode)  {
> >       struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
> > +     struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
> > +     const struct rzg2l_du_device_info *info = rcdu->info;
> >
> > -     if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
> > +     if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
> > +             return MODE_OK;
> > +
> > +     if (info->mode_clock_min && mode->clock < info->mode_clock_min)
>
> I will avoid checking the first part as it is mandatory for SoCs with DPI support
> and DPI check above make sure that this part of the code is reachable only for DPI
> output.
>
Will you fix up while applying or shall I send a new version?

Cheers,
Prabhakar
> > +             return MODE_CLOCK_LOW;
> > +     if (info->mode_clock_max && mode->clock > info->mode_clock_max)
>
> Same here.
>
> Cheers,
> Biju
>
> >               return MODE_CLOCK_HIGH;
> >
> >       return MODE_OK;
> > --
> > 2.54.0
>

RE: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 20 May 2026 09:14
> Subject: Re: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Wed, May 20, 2026 at 6:36 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: 19 May 2026 17:08
> > > Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic
> > > to per-SoC clock limits
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Move pixel clock validation from a fixed encoder check to per SoC
> > > constraints stored in rzg2l_du_device_info.
> > >
> > > Pixel clock limits differ across SoCs in the RZ DU family and cannot
> > > be expressed by a single shared rule. For example, RZ/G2UL and
> > > RZ/G2L limit the DPAD0 pixel clock to a narrow window, while other SoCs such as RZ/T2H require a
> wider operating range.
> > >
> > > Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info
> > > to describe the supported pixel clock range for each SoC. Update
> > > rzg2l_du_encoder_mode_valid() to check these bounds when evaluating
> > > DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls
> > > below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max.
> > >
> > > Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U)
> > > and RZ/G2L (R9A07G044) variants to a minimum of 20875 kHz and a
> > > maximum of
> > > 83500 kHz.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v3->v4:
> > > - Dropped per pad limits
> > > - Updated commit message to reflect the change in approach.
> > >
> > > v2->v3:
> > > - Moved clock limits from device_info to output_routing to allow
> > >   per-output constraints.
> > > - Updated commit message to reflect the change in approach.
> > >
> > > v1->v2:
> > > - Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed.
> > > ---
> > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c     | 6 +++++-
> > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h     | 4 ++++
> > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++-
> > >  3 files changed, 17 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_drv.c index
> > > 0fef33a5a089..1e4b9f38c55b 100644
> > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
> > >                       .port = 0,
> > >               },
> > >       },
> > > +     .mode_clock_min = 20875,
> > > +     .mode_clock_max = 83500,
> > >  };
> > >
> > >  static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info =
> > > { @@ -48,7 +50,9 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> > >                       .possible_outputs = BIT(0),
> > >                       .port = 1,
> > >               }
> > > -     }
> > > +     },
> > > +     .mode_clock_min = 20875,
> > > +     .mode_clock_max = 83500,
> > >  };
> > >
> > >  static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info =
> > > { diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > index 58806c2a8f2b..885558eb9547 100644
> > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing {
> > >   * struct rzg2l_du_device_info - DU model-specific information
> > >   * @channels_mask: bit mask of available DU channels
> > >   * @routes: array of CRTC to output routes, indexed by output
> > > (RZG2L_DU_OUTPUT_*)
> > > + * @mode_clock_min: minimum pixel clock in kHz
> > > + * @mode_clock_max: maximum pixel clock in kHz
> > >   */
> > >  struct rzg2l_du_device_info {
> > >       unsigned int channels_mask;
> > >       struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
> > > +     u32 mode_clock_min;
> > > +     u32 mode_clock_max;
> > >  };
> > >
> > >  #define RZG2L_DU_MAX_CRTCS           1
> > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_encoder.c index
> > > 0e567b57a408..56220139a149 100644
> > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
> > >                           const struct drm_display_mode *mode)  {
> > >       struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
> > > +     struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
> > > +     const struct rzg2l_du_device_info *info = rcdu->info;
> > >
> > > -     if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
> > > +     if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
> > > +             return MODE_OK;
> > > +
> > > +     if (info->mode_clock_min && mode->clock <
> > > + info->mode_clock_min)
> >
> > I will avoid checking the first part as it is mandatory for SoCs with
> > DPI support and DPI check above make sure that this part of the code
> > is reachable only for DPI output.
> >
> Will you fix up while applying or shall I send a new version?

I can take care of this if there are no other comments.

Cheers,
Biju

> 
> Cheers,
> Prabhakar
> > > +             return MODE_CLOCK_LOW;
> > > +     if (info->mode_clock_max && mode->clock >
> > > + info->mode_clock_max)
> >
> > Same here.
> >
> > Cheers,
> > Biju
> >
> > >               return MODE_CLOCK_HIGH;
> > >
> > >       return MODE_OK;
> > > --
> > > 2.54.0
> >

RE: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Biju Das]

Hi,

> -----Original Message-----
> From: Biju Das
> Sent: 20 May 2026 09:16
> Subject: RE: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits
> 
> Hi Prabhakar,
> 
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: 20 May 2026 09:14
> > Subject: Re: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic
> > to per-SoC clock limits
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Wed, May 20, 2026 at 6:36 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: 19 May 2026 17:08
> > > > Subject: [PATCH v4 4/5] drm: renesas: rz-du: Move mode_valid logic
> > > > to per-SoC clock limits
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Move pixel clock validation from a fixed encoder check to per SoC
> > > > constraints stored in rzg2l_du_device_info.
> > > >
> > > > Pixel clock limits differ across SoCs in the RZ DU family and
> > > > cannot be expressed by a single shared rule. For example, RZ/G2UL
> > > > and RZ/G2L limit the DPAD0 pixel clock to a narrow window, while
> > > > other SoCs such as RZ/T2H require a
> > wider operating range.
> > > >
> > > > Add mode_clock_min and mode_clock_max fields to
> > > > rzg2l_du_device_info to describe the supported pixel clock range
> > > > for each SoC. Update
> > > > rzg2l_du_encoder_mode_valid() to check these bounds when
> > > > evaluating
> > > > DPAD0 outputs, returning MODE_CLOCK_LOW when the pixel clock falls
> > > > below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max.
> > > >
> > > > Populate the pixel clock limits for both the RZ/G2UL (R9A07G043U)
> > > > and RZ/G2L (R9A07G044) variants to a minimum of 20875 kHz and a
> > > > maximum of
> > > > 83500 kHz.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v3->v4:
> > > > - Dropped per pad limits
> > > > - Updated commit message to reflect the change in approach.
> > > >
> > > > v2->v3:
> > > > - Moved clock limits from device_info to output_routing to allow
> > > >   per-output constraints.
> > > > - Updated commit message to reflect the change in approach.
> > > >
> > > > v1->v2:
> > > > - Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed.
> > > > ---
> > > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c     | 6 +++++-
> > > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h     | 4 ++++
> > > >  drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 9 ++++++++-
> > > >  3 files changed, 17 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_drv.c index
> > > > 0fef33a5a089..1e4b9f38c55b 100644
> > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c
> > > > @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = {
> > > >                       .port = 0,
> > > >               },
> > > >       },
> > > > +     .mode_clock_min = 20875,
> > > > +     .mode_clock_max = 83500,
> > > >  };
> > > >
> > > >  static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info
> > > > = { @@ -48,7 +50,9 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = {
> > > >                       .possible_outputs = BIT(0),
> > > >                       .port = 1,
> > > >               }
> > > > -     }
> > > > +     },
> > > > +     .mode_clock_min = 20875,
> > > > +     .mode_clock_max = 83500,
> > > >  };
> > > >
> > > >  static const struct rzg2l_du_device_info rzg2l_du_r9a09g057_info
> > > > = { diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > > b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > > index 58806c2a8f2b..885558eb9547 100644
> > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h
> > > > @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing {
> > > >   * struct rzg2l_du_device_info - DU model-specific information
> > > >   * @channels_mask: bit mask of available DU channels
> > > >   * @routes: array of CRTC to output routes, indexed by output
> > > > (RZG2L_DU_OUTPUT_*)
> > > > + * @mode_clock_min: minimum pixel clock in kHz
> > > > + * @mode_clock_max: maximum pixel clock in kHz
> > > >   */
> > > >  struct rzg2l_du_device_info {
> > > >       unsigned int channels_mask;
> > > >       struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];
> > > > +     u32 mode_clock_min;
> > > > +     u32 mode_clock_max;
> > > >  };
> > > >
> > > >  #define RZG2L_DU_MAX_CRTCS           1
> > > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > > b/drivers/gpu/drm/renesas/rz- du/rzg2l_du_encoder.c index
> > > > 0e567b57a408..56220139a149 100644
> > > > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c
> > > > @@ -50,8 +50,15 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder,
> > > >                           const struct drm_display_mode *mode)  {
> > > >       struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);
> > > > +     struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev);
> > > > +     const struct rzg2l_du_device_info *info = rcdu->info;
> > > >
> > > > -     if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
> > > > +     if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
> > > > +             return MODE_OK;
> > > > +
> > > > +     if (info->mode_clock_min && mode->clock <
> > > > + info->mode_clock_min)
> > >
> > > I will avoid checking the first part as it is mandatory for SoCs
> > > with DPI support and DPI check above make sure that this part of the
> > > code is reachable only for DPI output.
> > >
> > Will you fix up while applying or shall I send a new version?
> 
> I can take care of this if there are no other comments.

Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Cheers,
Biju

> 
> Cheers,
> Biju
> 
> >
> > Cheers,
> > Prabhakar
> > > > +             return MODE_CLOCK_LOW;
> > > > +     if (info->mode_clock_max && mode->clock >
> > > > + info->mode_clock_max)
> > >
> > > Same here.
> > >
> > > Cheers,
> > > Biju
> > >
> > > >               return MODE_CLOCK_HIGH;
> > > >
> > > >       return MODE_OK;
> > > > --
> > > > 2.54.0
> > >

RE: [PATCH v4 0/5] Add DU support for RZ/T2H and RZ/N2H SoCs

[Biju Das]

Hi,

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: 19 May 2026 17:08
> Subject: [PATCH v4 0/5] Add DU support for RZ/T2H and RZ/N2H SoCs
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Hi All,
> 
> This series adds support for the Display Unit (DU) on the RZ/T2H and RZ/N2H (R9A09G087) SoCs. The DU on
> these platforms is functionally similar to the RZ/G2UL DU but includes some SoC specific differences
> such as a single output port and explicit DPI output enable control. The series includes the following
> changes:
> 1. Add device tree bindings for the RZ/T2H and RZ/N2H DU variants,
>    including a new compatible string.
> 2. Make the DU reset control optional to allow probing on RZ/T2H
>    where the DU does not have a reset line.
> 3. Move pixel clock validation logic to per-SoC constraints in
>    rzg2l_du_device_info to accommodate different clock limits
>    across SoCs.
> 4. Implement support for the RZ/T2H DU variant in the driver,
>    including handling of the DPI output enable signal.
> 
> Patches are rebased on next-20260519 and apply on drm-next.
> 
> v3->v4:
> - Added Acked-by tag from Rob for patch #1
> - Added Reviewed-by tag from Rob for patches #2
> - Dropped per pad limits in patch #4 and added
>   a check to return early if the output is not DPAD0,
>   as the clock limits only apply to that output.
> - Updated commit message in patch #4
> 
> v2->v3:
> - Rebased on latest next-20260508.
> - Included Tommaso's patch to refuse port@1 for RZ/G2UL, which was
>   previously in a separate series.
> - Moved clock limits from device_info to output_routing to allow
>   per-output constraints.
> - Updated commit message for patch#4
> 
> v1->v2:
> - Dropped the "port" property in favor of "ports" with a single port@0
>   child, to align with the existing RZ/G2L bindings and simplify the
>   device tree structure.
> - Updated the commit message to reflect the change from "port" to "ports".
> - Dropped storing info pointer in struct rzg2l_du_encoder as it's not
>   needed.
> - Add Reviewed-by tags from Laurent for patches 2-4.
> - Rebase on latest next-20260507.
> 
> Cheers,
> Prabhakar
> 
> Lad Prabhakar (4):
>   dt-bindings: display: renesas,rzg2l-du: Add RZ/T2H and RZ/N2H support
>   drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support
>   drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits
>   drm: renesas: rz-du: Add support for RZ/T2H SoC
> 
> Tommaso Merciai (1):
>   dt-bindings: display: renesas,rzg2l-du: Refuse port@1 for RZ/G2UL
> 
>  .../bindings/display/renesas,rzg2l-du.yaml    | 21 +++++++++++++++++--
>  drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c |  9 ++++++--  drivers/gpu/drm/renesas/rz-
> du/rzg2l_du_drv.c  | 20 +++++++++++++++++-  drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h  | 14
> +++++++++++++  .../gpu/drm/renesas/rz-du/rzg2l_du_encoder.c  |  9 +++++++-
>  5 files changed, 67 insertions(+), 6 deletions(-)
> 
> --
> 2.54.0

Applied to drm-misc-next.

Cheers,
Biju

Claude review: Add DU support for RZ/T2H and RZ/N2H SoCs

[Claude Code Review Bot]

Overall Series Review

Subject: Add DU support for RZ/T2H and RZ/N2H SoCs
Author: Prabhakar <prabhakar.csengg@gmail.com>
Patches: 11
Reviewed: 2026-05-25T22:39:44.147399

---

This is a clean, well-structured 5-patch series adding Display Unit support for the Renesas RZ/T2H and RZ/N2H SoCs. The patches are properly ordered with DT bindings first, then preparatory driver refactoring, and the new SoC support last. The series has already received Reviewed-by from Laurent Pinchart and Rob Herring on the relevant patches. The code changes are small, focused, and follow existing patterns in the driver.

There are a couple of minor issues worth noting, but nothing that should block merging. The series is in good shape overall at v4.

---
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Claude review: dt-bindings: display: renesas, rzg2l-du: Refuse port@1 for RZ/G2UL

[Claude Code Review Bot]

Patch Review

**Status: Good**

Simple one-line addition to refuse `port@1` in the DT binding for RZ/G2UL, which only supports a single DPI output on port@0. This matches the existing pattern used for RZ/V2H(P) at the bottom of the same `allOf` block:

```yaml
            port@1: false
```

Already has Acked-by from Rob and Reviewed-by from Laurent. No issues.

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: renesas, rzg2l-du: Add RZ/T2H and RZ/N2H support

[Claude Code Review Bot]

Patch Review

**Status: Good, one minor observation**

Adds the new compatible strings and handles the structural differences:
- `renesas,r9a09g077-du` for RZ/T2H
- `renesas,r9a09g087-du` for RZ/N2H (with RZ/T2H as fallback)

The binding groups RZ/T2H with RZ/G2UL for the single-port constraint, which makes sense since both only support port@0 DPI:

```yaml
            enum:
              - renesas,r9a07g043u-du
              - renesas,r9a09g077-du
```

The `resets` handling is well done — making it conditional via `if/then/else`:

```yaml
  - if:
      properties:
        compatible:
          contains:
            const: renesas,r9a09g077-du
    then:
      properties:
        resets: false
    else:
      required:
        - resets
```

One observation: the `resets` property is removed from the top-level `required` list and made conditionally required via the `else` clause. This means any *future* SoC added to the binding without updating this `if/else` block would also get `resets` required, which is the safe default. Good design.

Note that patch 2 arrived out of order in the mbox (the mbox has it as the second message but with subject line "2/5" while the "3/5" patch arrived before it). This is just a mail delivery ordering artifact and doesn't affect the patches themselves.

---
Generated by Claude Code Patch Reviewer

Claude review: drm: renesas: rz-du: Make DU reset control optional for RZ/T2H support

[Claude Code Review Bot]

Patch Review

**Status: Good, minor nit**

Switches from `devm_reset_control_get_shared()` to `devm_reset_control_get_optional_shared()`. The existing error handling still works correctly since `_optional` returns NULL instead of an error when no reset is present, and `reset_control_assert()`/`reset_control_deassert()` are documented to be no-ops on NULL.

Minor nit: the error message `"can't get cpg reset\n"` will now only trigger for actual errors (not -ENOENT), but it might be slightly confusing since on RZ/T2H there's intentionally no reset. However, the `_optional` variant returns NULL for absent resets rather than an error, so this path only fires on genuine failures. This is fine.

---
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Claude review: drm: renesas: rz-du: Move mode_valid logic to per-SoC clock limits

[Claude Code Review Bot]

Patch Review

**Status: Good**

Refactors the hardcoded pixel clock check into per-SoC `mode_clock_min`/`mode_clock_max` fields in `rzg2l_du_device_info`. The old code:

```c
if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500)
    return MODE_CLOCK_HIGH;
```

becomes a table-driven check with an early return for non-DPAD0 outputs:

```c
if (renc->output != RZG2L_DU_OUTPUT_DPAD0)
    return MODE_OK;

if (info->mode_clock_min && mode->clock < info->mode_clock_min)
    return MODE_CLOCK_LOW;
if (info->mode_clock_max && mode->clock > info->mode_clock_max)
    return MODE_CLOCK_HIGH;
```

The zero-check (`info->mode_clock_min &&`) means SoCs that don't set these fields (like `r9a09g057`) will skip validation, which is correct since that SoC uses DSI0 output only (no DPAD0 route) and the early return would catch it anyway.

Existing RZ/G2UL and RZ/G2L both get `mode_clock_min = 20875` and `mode_clock_max = 83500`, preserving the existing 83500 max and adding the previously missing minimum. The addition of the minimum check is a slight functional change but is reasonable as a correction.

The trailing comma fix on the `r9a07g044` struct is a nice bonus cleanup:
```c
-	}
+	},
```

---
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Claude review: drm: renesas: rz-du: Add support for RZ/T2H SoC

[Claude Code Review Bot]

Patch Review

**Status: Good**

Adds the actual RZ/T2H support. Key additions:

1. **Feature flag infrastructure** — `RZG2L_DU_FEATURE_DPIO_OE` and the `rzg2l_du_has()` helper. The helper is clean:
```c
static inline bool rzg2l_du_has(struct rzg2l_du_device *rcdu,
                unsigned int feature)
{
    return rcdu->info->features & feature;
}
```

2. **DPI output enable** — In `rzg2l_du_start_stop()`, the RZ/T2H variant additionally asserts `DU_MCR0_DPI_EN` (BIT(0)):
```c
u32 val = DU_MCR0_DI_EN;

if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE))
    val |= DU_MCR0_DPI_EN;

writel(start ? val : 0, rcdu->mmio + DU_MCR0);
```

This correctly only sets `DPI_EN` when starting, and writes 0 when stopping (clearing both bits).

3. **Device info** for the new SoC with clock limits 5000–100000 kHz (wider than RZ/G2UL/G2L).

The `features` field is added to the struct doc comment in `rzg2l_du_drv.h`, which is good.

One thing to note: the patch series does not add the `r9a09g087` (RZ/N2H) compatible to the `of_device_id` table in the driver. This is fine since the DT binding specifies `renesas,r9a09g077-du` as the fallback for RZ/N2H, so the kernel will match on the RZ/T2H compatible. This is the standard Renesas pattern for compatible SoC variants.

**Overall verdict: The series looks ready to merge.** It's well-reviewed, follows established patterns, and the changes are correct and minimal.

---
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